Abstract: In some aspects, a hybrid quantum-classical computing platform may comprise: a first quantum processor unit (QPU); a second QPU; and a shared classical memory, the shared classical memory being connected to both the first QPU and the second QPU, wherein the shared classical memory is configured to share data between the first QPU and the second QPU. In some embodiments, the first QPU operates at a higher repetition rate and/or clock rate than the second QPU and the second QPU operates with a higher fidelity than the first QPU.

Abstract: Systems and techniques that facilitate backend quantum runtimes are provided. In various embodiments, a system can comprise a memory that can store computer-executable components. The system can further comprise a processor that can be operably coupled to the memory and that can execute the computer-executable components stored in the memory. In various embodiments, the computer-executable components can comprise an execution orchestration engine component that can parse a computer program into classical and quantum portions and that can host the computer program by instantiating a classical computing resource.

Abstract: Devices and methods that facilitate modular quantum systems with discreet levels of connectivity are provided. In various embodiments, a quantum computing device can comprise one or more modules comprising at least qubits, buses, and readout structures; a plurality of couplers, wherein the plurality of couplers comprises at least two couplers selected from a group consisting of: classical couplers, short-range couplers, and long-range couplers, that are adapted for coupling a plurality of the at least qubits, buses, and readout structures; and a connection from the one or more modules to one or more classical controllers external to a cryogenic environment comprising the one or more modules.

Abstract: One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to regional decoders for quantum error correction. Accordingly, a system can comprise a memory that can store computer executable components. The system can further comprise a processor that can execute at least one of the computer executable components that can map one or more regional decoders to one or more modules, wherein each of the one or more modules comprise one or more logical qubits, and wherein each of the one or more regional decoders operate on a region comprising one module and at least a subsection of another module. The at least one of the computer executable component can further coordinate activation of the one or more regional decoders by facilitating logical operations between a first logical qubit and a second logical qubit.

Abstract: In a general aspect, a quantum processor has a modular architecture. In some aspects, a modular quantum processor includes first and second quantum processor chips and a cap structure. The first quantum processor chip is supported on a substrate layer and includes a first plurality of qubit devices. The second quantum processor chip is supported on the substrate layer and includes a second plurality of qubit devices. The cap structure is supported on the first and second quantum processor chips and includes a coupler device that provides coupling between at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices. In some instances, the coupler device is an active coupler device that is configured to selectively couple at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices.

Abstract: In some aspects, a hybrid quantum-classical computing platform may comprise: a first quantum processor unit (QPU); a second QPU; and a shared classical memory, the shared classical memory being connected to both the first QPU and the second QPU, wherein the shared classical memory is configured to share data between the first QPU and the second QPU. In some embodiments, the first QPU operates at a higher repetition rate and/or clock rate than the second QPU and the second QPU operates with a higher fidelity than the first QPU.

Abstract: In a general aspect, a quantum processor has a modular architecture. In some aspects, a modular quantum processor includes first and second quantum processor chips and a cap structure. The first quantum processor chip is supported on a substrate layer and includes a first plurality of qubit devices. The second quantum processor chip is supported on the substrate layer and includes a second plurality of qubit devices. The cap structure is supported on the first and second quantum processor chips and includes a coupler device that provides coupling between at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices. In some instances, the coupler device is an active coupler device that is configured to selectively couple at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices.

Abstract: Devices and methods that facilitate modular quantum systems with discreet levels of connectivity are provided. In various embodiments, a quantum computing device can comprise one or more modules comprising at least qubits, buses, and readout structures; a plurality of couplers, wherein the plurality of couplers comprises at least two couplers selected from a group consisting of: classical couplers, short-range couplers, and long-range couplers, that are adapted for coupling a plurality of the at least qubits, buses, and readout structures; and a connection from the one or more modules to one or more classical controllers external to a cryogenic environment comprising the one or more modules.

Abstract: Systems and techniques that facilitate backend quantum runtimes are provided. In various embodiments, a system can comprise a memory that can store computer-executable components. The system can further comprise a processor that can be operably coupled to the memory and that can execute the computer-executable components stored in the memory. In various embodiments, the computer-executable components can comprise an execution orchestration engine component that can parse a computer program into classical and quantum portions and that can host the computer program by instantiating a classical computing resource.

Abstract: In a general aspect, a plurality of distinct quantum processor unit (QPU) instances are utilized to execute a quantum computation. Hybrid classical-quantum computing methods and systems are described which utilize the plurality of QPU instances in the execution of quantum computations.

Abstract: In a general aspect, a quantum processor has a modular architecture. In some aspects, a modular quantum processor includes first and second quantum processor chips and a cap structure. The first quantum processor chip is supported on a substrate layer and includes a first plurality of qubit devices. The second quantum processor chip is supported on the substrate layer and includes a second plurality of qubit devices. The cap structure is supported on the first and second quantum processor chips and includes a coupler device that provides coupling between at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices. In some instances, the coupler device is an active coupler device that is configured to selectively couple at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices.

Abstract: In some aspects, a hybrid quantum-classical computing platform may comprise: a first quantum processor unit (QPU); a second QPU; and a shared classical memory, the shared classical memory being connected to both the first QPU and the second QPU, wherein the shared classical memory is configured to share data between the first QPU and the second QPU. In some embodiments, the first QPU operates at a higher repetition rate and/or clock rate than the second QPU and the second QPU operates with a higher fidelity than the first QPU.

Abstract: Embodiments for providing an arbitrary control flow architecture for an arbitrary waveform generator (AWG) are generally described herein. In some embodiments, an arbitrary control flow instruction set defines control operations for generating an arbitrary waveform. A processor is arranged to execute the arbitrary control flow instruction set from data stored in a system memory to generate an arbitrary waveform. A system memory may include a low-latency memory and a high-latency memory, wherein a cache controller may use prediction mechanisms to reduce the latency of fetching instruction and waveform data by copying that data to the low-latency memory before it is requested.