Patents by Inventor Blake Travis

Blake Travis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145363
    Abstract: In examples, a semiconductor package comprises a semiconductor die having a device side comprising circuitry formed therein; a passivation layer abutting the device side; first and second horizontal metal members coupled to the device side by way of vias extending through the passivation layer, the first and second horizontal metal members having thicknesses ranging from 4 microns to 25 microns; first and second metal posts coupled to and vertically aligned with the first and second metal members, respectively, the first and second metal posts having vertical thicknesses ranging from 10 microns to 80 microns; first and second solder bumps coupled to the first and second metal posts, respectively; and a ball grid array (BGA) substrate coupled to the first and second solder bumps.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 2, 2024
    Inventors: Vivek SRIDHARAN, Yiqi TANG, Blake TRAVIS, Dibyajat MISHRA, Deepa KOTE
  • Publication number: 20230378146
    Abstract: An example microelectronic device package includes: a multilayer package substrate comprising routing conductors spaced by dielectric material, the multilayer package substrate having a device side surface and an opposing board side surface, and having a recessed portion extending from the device side surface and exposing routing conductors beneath the device side surface of the multilayer package substrate; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to the routing conductors; a passive component mounted to the routing conductors exposed in the recessed portion of the multilayer package substrate; and mold compound covering the semiconductor die, the passive component, and a portion of the multilayer package substrate.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 23, 2023
    Inventors: John Carlo Molina, Julian Carlo Barbadillo, Chun Ping Lo, Sylvester Ankamah-Kusi, Rajen Murugan, Thomas Kronenberg, Jonathan Noquil, Guangxu Li, Blake Travis, Jason Colte
  • Publication number: 20230378023
    Abstract: An electronic device includes a package structure, conductive leads partially exposed outside the package structure, and a semiconductor die having a semiconductor layer and a multilevel metallization structure, where the semiconductor die is enclosed by the package structure and the multilevel metallization structure includes a heater resistor, a sense resistor, and conductive metal features electrically coupled to respective terminals of the heater resistor and the sense resistor, with the conductive metal features electrically coupled to respective ones of the conductive leads.
    Type: Application
    Filed: September 23, 2022
    Publication date: November 23, 2023
    Inventors: Vinod Rai, Archana Venugopal, Blake Travis