Abstract: An electronic device includes a package structure, conductive leads partially exposed outside the package structure, and a semiconductor die having a semiconductor layer and a multilevel metallization structure, where the semiconductor die is enclosed by the package structure and the multilevel metallization structure includes a heater resistor, a sense resistor, and conductive metal features electrically coupled to respective terminals of the heater resistor and the sense resistor, with the conductive metal features electrically coupled to respective ones of the conductive leads.

Abstract: A semiconductor die comprises a first bump structure. The first bump structure comprises a pillar portion and a solder portion attached to the pillar portion. The first bump structure is a signal bump structure of the semiconductor die that transmits electrical signals between the semiconductor die and a leadframe. The semiconductor die further comprises a second bump structure. The second bump structure comprises a base portion, a plurality of pillar portions on the base portion, and a plurality of solder portions attached to the plurality of pillar portions. The second bump structure is a power bump structure of the semiconductor die that transmits power between the semiconductor die and the leadframe.

Abstract: In examples, a semiconductor package includes a semiconductor die having a device side in which circuitry is formed; multiple copper posts coupled to the device side of the semiconductor die; a substrate coupled to the multiple copper posts by solder joints, the substrate comprising: cylindrical copper pillars extending from the solder joints on a top surface of the substrate to a bottom surface of the substrate, the copper pillars having circular or ovoid bottom surfaces exposed to the bottom surface of the substrate; and a build-up film between and physically contacting the copper pillars. The package also includes a mold compound physically contacting the semiconductor die, the multiple copper posts, and the top surface of the substrate.

Abstract: An electronic device includes a substrate, a first metal layer embedded in a first surface of the substrate and a second metal layer embedded in a second surface of the substrate opposite that of the first surface. A via layer is disposed between the first metal layer and the second metal layer and electrically connects the first metal layer and the second metal layer. The via layer includes a moisture dissipation feature. A die is attached to the first metal layer and a mold compound is formed over the die.

Abstract: An electronic device includes a die, a ground die attach pad, and a power supply die attach pad. Wire bonds connect ground nets from the die to the ground die attach pad. Additional wire bonds connect power supply nets from the die to the power supply die attach pad. Additional wire bonds connect signal nets from the die to pins on a periphery of the electronic device.

Abstract: An electronic device includes a substrate having conductive features, and a semiconductor die having conductive terminals along a first side, and an indent that extends into an opposite second side, the conductive terminals attached to respective ones of the conductive features of the substrate. A method of fabricating an electronic device includes forming an indent into a second side of a semiconductor die and attaching conductive terminals along an opposite first side of the semiconductor die to respective conductive features of a substrate.

Abstract: An electronic device includes a leadframe, where the leadframe includes inner leads, external leads, and die attach portions. The leadframe has channels defined at a junction between the die attach portions and the inner leads, where the channel mitigates crack propagation along a path of the die attach portions. A die assembly is attached to the die attach portions and copper pillars are provided to connect the die assembly to the die attach portions. A mold compound encapsulates the die assembly, the inner leads, the die attach portions, and the copper pillars.

Abstract: An electronic device includes a multilevel package substrate having opposite first and second sides, a semiconductor die attached to the first side, a first molded package structure on the first side, and a second molded package structure on the second side and spaced apart from the first molded package structure. A method of fabricating an electronic device includes attaching a semiconductor die to a first side of a soldermaskless multilevel package substrate, forming a first molded package structure on the first side of the multilevel package substrate, and forming a second molded package structure on an opposite second side of the multilevel package substrate and spaced apart from the first molded package structure.

Abstract: In examples, a semiconductor package comprises a semiconductor die having a device side comprising circuitry formed therein; a passivation layer abutting the device side; first and second horizontal metal members coupled to the device side by way of vias extending through the passivation layer, the first and second horizontal metal members having thicknesses ranging from 4 microns to 25 microns; first and second metal posts coupled to and vertically aligned with the first and second metal members, respectively, the first and second metal posts having vertical thicknesses ranging from 10 microns to 80 microns; first and second solder bumps coupled to the first and second metal posts, respectively; and a ball grid array (BGA) substrate coupled to the first and second solder bumps.

Abstract: An electronic device includes a package structure, conductive leads partially exposed outside the package structure, and a semiconductor die having a semiconductor layer and a multilevel metallization structure, where the semiconductor die is enclosed by the package structure and the multilevel metallization structure includes a heater resistor, a sense resistor, and conductive metal features electrically coupled to respective terminals of the heater resistor and the sense resistor, with the conductive metal features electrically coupled to respective ones of the conductive leads.

Abstract: An example microelectronic device package includes: a multilayer package substrate comprising routing conductors spaced by dielectric material, the multilayer package substrate having a device side surface and an opposing board side surface, and having a recessed portion extending from the device side surface and exposing routing conductors beneath the device side surface of the multilayer package substrate; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to the routing conductors; a passive component mounted to the routing conductors exposed in the recessed portion of the multilayer package substrate; and mold compound covering the semiconductor die, the passive component, and a portion of the multilayer package substrate.