Patents by Inventor Blas Cuesta

Blas Cuesta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9645942
    Abstract: A method to request memory from a far memory cache and implement, at an operating system (OS) level, a fully associative cache on the requested memory. The method includes pinning the working set of a program into the requested memory (pin buffer) so that it is not evicted due to cache conflicts and is served from the fast cache and not the slower next level memory. The requested memory extends the physical address space and is visible to and managed by the OS. The OS has the ability to make the requested memory visible to the user programs. The OS has the ability to manage the requested memory from the far memory cache as both a fully associative cache and a set associative cache.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Ferad Zyulkyarov, Nevin Hyuseinova, Qiong Cai, Blas Cuesta, Serkan Ozdemir, Marios Nicolaides
  • Patent number: 9558120
    Abstract: Techniques and mechanism to provide a cache of cache tags in determining an access to cached data. In an embodiment, a tag storage stores a first set including tags associated with respective data locations of a cache memory. A cache of cache tags store a subset of tags stored by the tag storage. In response to any determination that a tag of the first set is to be stored to the cache of cache tags, all tags of the first set are stored to the first portion. Any storage of tags of the first set to the cache of cache tags includes storage of the tags of the first set to only a first portion of the cache of cache tags. In another embodiment, a replacement table is maintained for use in determining, based on an indicated level of activity for a set of the cache of cache tags, whether the set is to be selected for eviction and replacement of cached tags.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: January 31, 2017
    Assignee: Intel Corporation
    Inventors: Dyer Rolan, Nevin Hyuseinova, Blas A. Cuesta, Qiong Cai
  • Patent number: 9286237
    Abstract: Embodiments of methods, apparatuses, and storage media for memory imbalance prediction-based cache memory management are disclosed herein. In one instance, the apparatus may include a memory controller associated with a memory having a plurality of storage units. The memory controller may include logic configured to determine whether the memory enters into an imbalance state based at least in part on a difference in numbers of pending access requests to different storage units, and cause an adjustment of replacement management of a cache memory, based at least in part on a result of the determination. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 15, 2016
    Assignee: Intel Corporation
    Inventors: Qiong Cai, Dyer Rolan, Blas Cuesta, Ferad Zyulkyarov, Serkan Ozdemir, Marios Nicolaides
  • Publication number: 20150278096
    Abstract: Techniques and mechanism to provide a cache of cache tags in determining an access to cached data. In an embodiment, a tag storage stores a first set including tags associated with respective data locations of a cache memory. A cache of cache tags store a subset of tags stored by the tag storage. In response to any determination that a tag of the first set is to be stored to the cache of cache tags, all tags of the first set are stored to the first portion. Any storage of tags of the first set to the cache of cache tags includes storage of the tags of the first set to only a first portion of the cache of cache tags. In another embodiment, a replacement table is maintained for use in determining, based on an indicated level of activity for a set of the cache of cache tags, whether the set is to be selected for eviction and replacement of cached tags.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: Dyer Rolan, Nevin Hyuseinova, Blas A. Cuesta, Qiong Cai
  • Publication number: 20150227469
    Abstract: A method to request memory from a far memory cache and implement, at an operating system (OS) level, a fully associative cache on the requested memory. The method includes pinning the working set of a program into the requested memory (pin buffer) so that it is not evicted due to cache conflicts and is served from the fast cache and not the slower next level memory. The requested memory extends the physical address space and is visible to and managed by the OS. The OS has the ability to make the requested memory visible to the user programs. The OS has the ability to manage the requested memory from the far memory cache as both a fully associative cache and a set associative cache.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 13, 2015
    Inventors: Ferad Zyulkyarov, Nevin Hyuseinova, Qiong Cai, Blas Cuesta, Serkan Ozdemir, Marios Nicolaides
  • Patent number: 9003126
    Abstract: Techniques and mechanisms for adaptively changing between replacement policies for selecting lines of a cache for eviction. In an embodiment, evaluation logic determines a value of a performance metric which is for writes to a non-volatile memory. Based on the determined value of the performance metric, a parameter value of a replacement policy is determined. In another embodiment, cache replacement logic performs a selection of a line of cache for data eviction, where the selection is in response to the policy unit providing an indication of the determined parameter value.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: April 7, 2015
    Assignee: Intel Corporation
    Inventors: Qiong Cai, Nevin Hyuseinova, Serkan Ozdemir, Ferad Zyulkyarov, Marios Nicolaides, Blas Cuesta
  • Publication number: 20140258605
    Abstract: Embodiments of methods, apparatuses, and storage media for memory imbalance prediction-based cache memory management are disclosed herein. In one instance, the apparatus may include a memory controller associated with a memory having a plurality of storage units. The memory controller may include logic configured to determine whether the memory enters into an imbalance state based at least in part on a difference in numbers of pending access requests to different storage units, and cause an adjustment of replacement management of a cache memory, based at least in part on a result of the determination. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Inventors: Qiong Cai, Dyer Rolan, Blas Cuesta, Ferad Zyulkyarov, Serkan Ozdemir, Marios Nicolaides
  • Publication number: 20140189243
    Abstract: A coarse-grained cache line may be associated with a way from a set in a cache. A first sector of the coarse-grained cache line may be stored in the way. The coarse-grained cache line may include a predetermined number of sectors. A fine-grained cache line may be associated with the way. A second sector of the fine-grained cache line may be stored in the way. The fine-grained cache line may include a predetermined number of sectors. The predetermined number of sectors in the fine-grained cache line may be lower than the predetermined number of sectors in the coarse-grained cache line.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Blas CUESTA, Qiong CAI, Nevin HYUSEINOVA, Serkan OZDEMIR, Marios NICOLAIDES, Ferad ZYULKYAROV
  • Publication number: 20140089559
    Abstract: Techniques and mechanisms for adaptively changing between replacement policies for selecting lines of a cache for eviction. In an embodiment, evaluation logic determines a value of a performance metric which is for writes to a non-volatile memory. Based on the determined value of the performance metric, a parameter value of a replacement policy is determined. In another embodiment, cache replacement logic performs a selection of a line of cache for data eviction, where the selection is in response to the policy unit providing an indication of the determined parameter value.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 27, 2014
    Inventors: Qiong Cai, Nevin Hyuseinova, Serkan Ozdemir, Ferad Zyulkyarov, Marios Nicolaides, Blas Cuesta