Abstract: A field effect transistor includes a substrate; an electron channel layer disposed on the substrate; a barrier layer disposed on the electron channel layer; a hole channel layer disposed on the barrier layer; a p-type doped semiconductor material layer disposed on the hole channel layer; a source electrode including a first portion in ohmic contact with the electron channel layer and a second portion in ohmic contact with the p-type doped semiconductor material layer; a drain electrode in ohmic contact with the electron channel layer; and a gate electrode disposed facing the p-type doped semiconductor material layer, between the source and drain electrodes.

Abstract: A test structure for a buried gate transistor includes a substrate, a first test contact located on one side of a first transistor contact, a second test contact located on one side of a second transistor contact, and a layer buried in the substrate, having a doping greater than or equal to 1018 cm?3, and having a face which is tangent to the buried part of the gate. A first insulation structure is disposed between the first test contact and the first transistor contact and a second insulation structure is disposed between the second test contact and the second transistor contact. The first and second test contacts each have an end connected to the buried layer.

Abstract: A transistor including a gate region penetrating into a first gallium nitride layer, wherein a second electrically-conductive layer coats at least one of the sides of said gate region.

Abstract: An electronic device including semiconductor region located on a gallium nitride layer, two electrodes, located on either side of and insulated from the semiconductor region, the electrodes partially penetrating into the gallium nitride layer, and two lateral MOS transistors formed inside and on top of the semiconductor region.

Abstract: A GaN-based power transistor including: a stack of layers in a vertical direction (z), the stack including, from an upper surface of the stack: a first AlGaN-based barrier), a GaN-based layer, and a second AlGaN-based barrier; and a gate pattern including: a metal gate, and a gate dielectric electrically insulating the metal gate from the stack, the metal gate being in contact with a bottom part and a wall part of the gate dielectric, the gate pattern passing through the first AlGaN-based barrier, then totally passing through the GaN-based layer and at least partially through the second AlGaN-based barrier, in the vertical direction (z), such that the second AlGaN-based barrier has a concentration of aluminium [Al]2 of less than or equal to 8% at.

Abstract: Electron gas transistor of normally open type, includes a first semiconductor layer laid out along a layer plane and a second semiconductor layer formed on the first semiconductor layer and laid out along the layer plane, the first and second semiconductor layers forming an electron gas layer at the interface thereof; a third semiconductor layer with P type doping formed on the second semiconductor layer and laid out along the layer plane, a first zone with N type doping of which a part is arranged within the thickness of the third semiconductor layer, the first zone-delimiting a source zone; a second zone with N or metal type doping having at least one part arranged in the second semiconductor layer; a source electrode formed on the source zone; a drain electrode formed on the first semiconductor layer; and a gate located between the source electrode and the second zone.

Abstract: A transistor comprising a gallium nitride layer having a first gate electrode partially penetrating into it, having: a first side coated with a first thickness of a first insulating material and of a second insulating material; and with a second thickness of a conductive material; and a bottom coated with a third thickness, smaller than the first thickness, of the first insulating material.

Abstract: A device including a first transistor, having a gate region partially penetrating into a gallium nitride layer, and a second transistor located inside of the gate region of the first transistor.

Abstract: Electron gas transistor of normally open type, includes a first semiconductor layer laid out along a layer plane and a second semiconductor layer formed on the first semiconductor layer and laid out along the layer plane, the first and second semiconductor layers forming an electron gas layer at the interface thereof; a third semiconductor layer with P type doping formed on the second semiconductor layer and laid out along the layer plane, a first zone with N type doping of which a part is arranged within the thickness of the third semiconductor layer, the first zone-delimiting a source zone; a second zone with N or metal type doping having at least one part arranged in the second semiconductor layer; a source electrode formed on the source zone; a drain electrode formed on the first semiconductor layer; and a gate located between the source electrode and the second zone.