Patents by Inventor Blue Larn

Blue Larn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-volatile memory and manufacturing method thereof
    Patent number: 7144777
    Abstract: A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: December 5, 2006
    Assignee: United Microelectronics Corp.
    Inventors: Tzung-Han Lee, Wen-Jeng Lin, Kuang-Pi Lee, Blue Larn
  • NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF
    Publication number: 20060192241
    Abstract: A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.
    Type: Application
    Filed: February 25, 2005
    Publication date: August 31, 2006
    Inventors: Tzung-Han Lee, Wen-Jeng Lin, Kuang-Pi Lee, Blue Larn