Abstract: The present disclosure provides a wafer chuck including a substrate and a heating/cooling wafer. The substrate includes a first surface facing a wafer to be carried and a second surface opposite to the first surface. The heating/cooling wafer is disposed on the first surface of the substrate and includes a plurality of heating/cooling units arranged in an array. In a direction perpendicular to the first surface, the positions of the heating/cooling units and the positions of a plurality of dies included in the wafer to be carried are corresponded with each other, and the heating/cooling units can heat or cool the corresponding dies individually.

Abstract: A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.

Abstract: A physical unclonable function (PUF) generator structure including a substrate and a PUF generator is provided. The PUF generator includes a first electrode layer, a second electrode layer, a first dielectric layer, a first contact, a second contact, and a third contact. The first electrode layer is disposed on the substrate. The second electrode layer is disposed on the first electrode layer. The first dielectric layer is disposed between the first electrode layer and the second electrode layer. The first contact and the second contact are electrically connected to the first electrode layer and are separated from each other. The third contact is electrically connected to the second electrode layer.

Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, and a P-type gallium nitride layer is provided. The first barrier layer is disposed on the channel layer. The P-type gallium nitride layer is disposed on the first barrier layer. The first thickness of the first barrier layer located directly under the P-type gallium nitride layer is greater than the second thickness of the first barrier layer located on two sides of the P-type gallium nitride layer.

Abstract: A semiconductor structure including a substrate, a through-substrate via (TSV), a first insulating layer, an isolation structure, and a capacitor is provided. The substrate includes a TSV region and a keep-out zone (KOZ) adjacent to each other. The TSV is located in the substrate in the TSV region. The first insulating layer is located between the TSV and the substrate. The isolation structure is located in the substrate in the KOZ. There are trenches in the isolation structure. A capacitor is located on the isolation structure and in the trenches.

Abstract: A method for manufacturing a non-volatile memory device includes forming a device isolation structure in a substrate, forming a floating gate, an inner layer dielectric (ILD) layer, and a floating gate contact on the substrate, and forming an interconnect structure on the ILD layer. The interconnect structure includes alternately stacked metal layers and inter metal dielectric (IMD) layers and vias connecting the upper and lower metal layers. In the method, after the ILD layer is formed, first and second comb-shaped contacts are simultaneously formed in at least one of the ILD layer and the IMD layers above the device isolation structure, wherein the first comb-shaped contact is a floating gate extension part, and the second comb-shaped contact is a control gate. During the forming of the interconnect structure, a structure is simultaneously formed for electrically connecting the floating gate extension part to the floating gate contact.

Abstract: A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.

Abstract: A method for manufacturing a non-volatile memory device includes forming a device isolation structure in a substrate, forming a floating gate, an inner layer dielectric (ILD) layer, and a floating gate contact on the substrate, and forming an interconnect structure on the ILD layer. The interconnect structure includes alternately stacked metal layers and inter metal dielectric (IMD) layers and vias connecting the upper and lower metal layers. In the method, after the ILD layer is formed, first and second comb-shaped contacts are simultaneously formed in at least one of the ILD layer and the IMD layers above the device isolation structure, wherein the first comb-shaped contact s a floating gate extension part, and the second comb-shaped contact is a control gate. During the forming of the interconnect structure, a structure is simultaneously formed for electrically connecting the floating gate extension part to the floating gate contact.

Abstract: A method for manufacturing a non-volatile memory device includes forming a device isolation structure in a substrate, forming a floating gate, an inner layer dielectric (ILD) layer, and a floating gate contact on the substrate, and forming an interconnect structure on the ILD layer. The interconnect structure includes alternately stacked metal layers and inter metal dielectric (IMD) layers and vias connecting the upper and lower metal layers. In the method, after the ILD layer is formed, first and second comb-shaped contacts are simultaneously formed in at least one of the ILD layer and the IMD layers above the device isolation structure, wherein the first comb-shaped contact is a floating gate extension part, and the second comb-shaped contact is a control gate. During the forming of the interconnect structure, a structure is simultaneously formed for electrically connecting the floating gate extension part to the floating gate contact.

Abstract: A method for manufacturing a non-volatile memory device includes forming a device isolation structure in a substrate, forming a floating gate, an inner layer dielectric (ILD) layer, and a floating gate contact on the substrate, and forming an interconnect structure on the ILD layer. The interconnect structure includes alternately stacked metal layers and inter metal dielectric (IMD) layers and vias connecting the upper and lower metal layers. In the method, after the ILD layer is formed, first and second comb-shaped contacts are simultaneously formed in at least one of the ILD layer and the IMD layers above the device isolation structure, wherein the first comb-shaped contact is a floating gate extension part, and the second comb-shaped contact is a control gate. During the forming of the interconnect structure, a structure is simultaneously formed for electrically connecting the floating gate extension part to the floating gate contact.

Abstract: A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes first well regions and a second well region in a semiconductor substrate; first transistors within the first wells; second transistors within the second well; and bit lines. The first wells are separately arranged along a first direction and a second direction. The second well continuously spreads between the first wells. Each first transistor and one of the second transistors are adjacent and connected to each other via a common source or common drain. The common drain or common source is electrically connected to a storage capacitor, and the electrically connected first and second transistors as well as the storage capacitor form a memory cell. The bit lines respectively extend between adjacent rows of the first wells. Adjacent memory cells arranged along the second direction are electrically connected to the same bit line.

Abstract: A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes first well regions and a second well region in a semiconductor substrate; first transistors within the first wells; second transistors within the second well; and bit lines. The first wells are separately arranged along a first direction and a second direction. The second well continuously spreads between the first wells. Each first transistor and one of the second transistors are adjacent and connected to each other via a common source or common drain. The common drain or common source is electrically connected to a storage capacitor, and the electrically connected first and second transistors as well as the storage capacitor form a memory cell. The bit lines respectively extend between adjacent rows of the first wells. Adjacent memory cells arranged along the second direction are electrically connected to the same bit line.

Abstract: A memory structure including first and second transistors, an isolation structure and a capacitor and a manufacturing method thereof are provided. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extensions are extended from the body portion into the substrate at two sides of the isolation structure and connected to the source/drain regions of the first and the second transistors, respectively. The widths of first and second extension portions are decreased downward from a top surface of the isolation structure.

Abstract: A memory structure including first and second transistors, an isolation structure and a capacitor and a manufacturing method thereof are provided. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extensions are extended from the body portion into the substrate at two sides of the isolation structure and connected to the source/drain regions of the first and the second transistors, respectively. The widths of first and second extension portions are decreased downward from a top surface of the isolation structure.