Abstract: A physical unclonable function (PUF) generator structure including a substrate and a PUF generator is provided. The PUF generator includes a first electrode layer, a second electrode layer, a first dielectric layer, a first contact, a second contact, and a third contact. The first electrode layer is disposed on the substrate. The second electrode layer is disposed on the first electrode layer. The first dielectric layer is disposed between the first electrode layer and the second electrode layer. The first contact and the second contact are electrically connected to the first electrode layer and are separated from each other. The third contact is electrically connected to the second electrode layer.

Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, and a P-type gallium nitride layer is provided. The first barrier layer is disposed on the channel layer. The P-type gallium nitride layer is disposed on the first barrier layer. The first thickness of the first barrier layer located directly under the P-type gallium nitride layer is greater than the second thickness of the first barrier layer located on two sides of the P-type gallium nitride layer.

Abstract: A semiconductor structure including a substrate, a through-substrate via (TSV), a first insulating layer, an isolation structure, and a capacitor is provided. The substrate includes a TSV region and a keep-out zone (KOZ) adjacent to each other. The TSV is located in the substrate in the TSV region. The first insulating layer is located between the TSV and the substrate. The isolation structure is located in the substrate in the KOZ. There are trenches in the isolation structure. A capacitor is located on the isolation structure and in the trenches.

Abstract: A container with a handle includes a container body. The container body has a peripheral edge extending outward to form a ring portion. The ring portion is provided with a first slot penetrating through the ring portion. The first slot cuts the ring portion to form a first handle portion and a first edge portion completely connected to the container body. In addition, the ring portion is further provided with a second slot penetrating through the ring portion. The first slot and the second slot are respectively located on two opposite sides of the ring portion. The second slot cuts the ring portion to form a second handle portion and a second edge portion completely connected to the container body. The first handle portion and the second handle portion each have two ends connected to the container body and may be pulled up as the handle.

Abstract: A method for manufacturing a non-volatile memory device includes forming a device isolation structure in a substrate, forming a floating gate, an inner layer dielectric (ILD) layer, and a floating gate contact on the substrate, and forming an interconnect structure on the ILD layer. The interconnect structure includes alternately stacked metal layers and inter metal dielectric (IMD) layers and vias connecting the upper and lower metal layers. In the method, after the ILD layer is formed, first and second comb-shaped contacts are simultaneously formed in at least one of the ILD layer and the IMD layers above the device isolation structure, wherein the first comb-shaped contact is a floating gate extension part, and the second comb-shaped contact is a control gate. During the forming of the interconnect structure, a structure is simultaneously formed for electrically connecting the floating gate extension part to the floating gate contact.

Abstract: A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.

Abstract: A method for manufacturing a non-volatile memory device includes forming a device isolation structure in a substrate, forming a floating gate, an inner layer dielectric (ILD) layer, and a floating gate contact on the substrate, and forming an interconnect structure on the ILD layer. The interconnect structure includes alternately stacked metal layers and inter metal dielectric (IMD) layers and vias connecting the upper and lower metal layers. In the method, after the ILD layer is formed, first and second comb-shaped contacts are simultaneously formed in at least one of the ILD layer and the IMD layers above the device isolation structure, wherein the first comb-shaped contact s a floating gate extension part, and the second comb-shaped contact is a control gate. During the forming of the interconnect structure, a structure is simultaneously formed for electrically connecting the floating gate extension part to the floating gate contact.

Abstract: A method for manufacturing a non-volatile memory device includes forming a device isolation structure in a substrate, forming a floating gate, an inner layer dielectric (ILD) layer, and a floating gate contact on the substrate, and forming an interconnect structure on the ILD layer. The interconnect structure includes alternately stacked metal layers and inter metal dielectric (IMD) layers and vias connecting the upper and lower metal layers. In the method, after the ILD layer is formed, first and second comb-shaped contacts are simultaneously formed in at least one of the ILD layer and the IMD layers above the device isolation structure, wherein the first comb-shaped contact is a floating gate extension part, and the second comb-shaped contact is a control gate. During the forming of the interconnect structure, a structure is simultaneously formed for electrically connecting the floating gate extension part to the floating gate contact.

Abstract: A method for manufacturing a non-volatile memory device includes forming a device isolation structure in a substrate, forming a floating gate, an inner layer dielectric (ILD) layer, and a floating gate contact on the substrate, and forming an interconnect structure on the ILD layer. The interconnect structure includes alternately stacked metal layers and inter metal dielectric (IMD) layers and vias connecting the upper and lower metal layers. In the method, after the ILD layer is formed, first and second comb-shaped contacts are simultaneously formed in at least one of the ILD layer and the IMD layers above the device isolation structure, wherein the first comb-shaped contact is a floating gate extension part, and the second comb-shaped contact is a control gate. During the forming of the interconnect structure, a structure is simultaneously formed for electrically connecting the floating gate extension part to the floating gate contact.

Abstract: A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes first well regions and a second well region in a semiconductor substrate; first transistors within the first wells; second transistors within the second well; and bit lines. The first wells are separately arranged along a first direction and a second direction. The second well continuously spreads between the first wells. Each first transistor and one of the second transistors are adjacent and connected to each other via a common source or common drain. The common drain or common source is electrically connected to a storage capacitor, and the electrically connected first and second transistors as well as the storage capacitor form a memory cell. The bit lines respectively extend between adjacent rows of the first wells. Adjacent memory cells arranged along the second direction are electrically connected to the same bit line.

Abstract: A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes first well regions and a second well region in a semiconductor substrate; first transistors within the first wells; second transistors within the second well; and bit lines. The first wells are separately arranged along a first direction and a second direction. The second well continuously spreads between the first wells. Each first transistor and one of the second transistors are adjacent and connected to each other via a common source or common drain. The common drain or common source is electrically connected to a storage capacitor, and the electrically connected first and second transistors as well as the storage capacitor form a memory cell. The bit lines respectively extend between adjacent rows of the first wells. Adjacent memory cells arranged along the second direction are electrically connected to the same bit line.

Abstract: A memory structure including first and second transistors, an isolation structure and a capacitor and a manufacturing method thereof are provided. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extensions are extended from the body portion into the substrate at two sides of the isolation structure and connected to the source/drain regions of the first and the second transistors, respectively. The widths of first and second extension portions are decreased downward from a top surface of the isolation structure.

Abstract: A memory structure including first and second transistors, an isolation structure and a capacitor and a manufacturing method thereof are provided. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extensions are extended from the body portion into the substrate at two sides of the isolation structure and connected to the source/drain regions of the first and the second transistors, respectively. The widths of first and second extension portions are decreased downward from a top surface of the isolation structure.

Abstract: A flexible supercapacitor and a preparation method thereof are provided. The flexible supercapacitor includes a polymer-based solid electrolyte layer, two active layers respectively disposed on opposite surfaces of the polymer-based solid electrolyte layer, and two electron conducting layers disposed on outer exposed surfaces of the two active layers.

Abstract: A method for decreasing resistivity of an electrolyte for an electric double-layer capacitor is provided. In this method, an aqueous electrolyte solution comprising LiNO3 and LiOH in a molar ratio of 1:9 to 9:1 is prepared first, and then purged with nitrogen or oxygen. An electric double-layer capacitor having the gas-purging aqueous electrolyte solution above is also provided.

Abstract: A shoe apparatus includes a shoe, a power supply and a wireless transmitter. The shoe is to be worn by a user. The power supply is provided in the shoe for generation and storage of electricity. The power supply includes a battery, a first generator unit electrically connected to the battery and a second generator unit electrically connected to the battery. The wireless transmitter is provided in the shoe and electrically connected to the power supply for wireless communication of data with a remote device.

Abstract: SPEEK solid electrolytes and preparation methods thereof are provided. The SPEEK solid electrolyte comprises sulfonated polyetheretherketone (SPEEK), an electrolyte, and a solvent. The electrolyte is a lithium salt.

Abstract: A flexible supercapacitor and a preparation method thereof are provided. The flexible supercapacitor includes a polymer-based solid electrolyte layer, two active layers respectively disposed on opposite surfaces of the polymer-based solid electrolyte layer, and two electron conducting layers disposed on outer exposed surfaces of the two active layers.

Abstract: A thermally enhanced light emitting device package includes a substrate, a chip attached to the substrate, an encapsulant overlaid on the chip, and a plurality of non-electrically conductive carbon nanocapsules mixed in the encapsulant to facilitate heat dissipation from the chip.

Abstract: Polymer-based solid electrolytes and preparation methods thereof are provided. The polymer-based solid electrolyte comprises a polymer, an electrolyte, and a solvent. The polymer of the solid electrolyte can be polyvinyl alcohol (PVA) or sulfonated polyetheretherketone (SPEEK). The electrolyte is a lithium salt.