Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

Abstract: The present invention relates to a method of treating moderate or severe symptoms of COVID-19 using a plant composition. The plant composition comprises Prepared Monkshood Daughter Root (Aconitum carmichaelii), Fragrant Solomonseal Rhizome (Polygonatum odoratum), Indian Bread (Poria cocos), Pinellia tuber (Pinellia ternata), Oriental Wormwood Herb (Artemisia scoparia), Scutellaria Root (Scutellaria baicalensis), Mongolian Snakegourd Fruit (Trichosanthes kirilowii), Magnolia Bark (Magnolia officinalis), Heartleaf Houttuynia Herb (Houttuynia cordata), and Baked Licorice Root and Rhizome (Glycyrrhiza glabra), which is used as a traditional Chinese medicine composition.

Abstract: An apparatus includes a memory unit configured to store nonzero entries of a first array and nonzero entries of a second array based on a sparse matrix format; and an index module configured to select the common nonzero entries of the neurons and the corresponding weights. Since the values of the nonzero entries of the neurons and corresponding weights are selected and accessed, the data load and movement from the memory unit can be reduced to save power consumption. In addition, for a sparse neuronal network model with a large scale, through the operations of the index module, the computation regarding a great amount of zero entries can be scattered to improve overall computation speed of a neural network.

Abstract: A low density parity check (LDPC) decoding method and a decoding apparatus are provided. The method includes following steps. Based on M edges of a Tanner graph related to a parity check matrix, each of the edges is associated with one of a plurality of threads, such that each of the threads is corresponding to one of a plurality of edge identifies. When executing one of the threads, data in a shared memory is accessed according to the edge identifier of the one of the threads, so as to update a plurality of passing massages respectively corresponding to the edges in the shared memory. Thereby, high computation parallelism and fully-coalesced data accesses can be achieved.

Abstract: A low density parity check (LDPC) decoding method and a decoding apparatus are provided. The method includes following steps. Based on M edges of a Tanner graph related to a parity check matrix, each of the edges is associated with one of a plurality of threads, such that each of the threads is corresponding to one of a plurality of edge identifies. When executing one of the threads, data in a shared memory is accessed according to the edge identifier of the one of the threads, so as to update a plurality of passing massages respectively corresponding to the edges in the shared memory. Thereby, high computation parallelism and fully-coalesced data accesses can be achieved.

Abstract: A method for accessing a multi-port memory module comprising a plurality of banks is provided, wherein the plurality of banks comprise at least a first bank, a second bank and a reference bank, and the method comprises: when first data is requested to be written into the first bank, reading reference data from the reference bank, and encoding the first data with the reference data to generate first encoded data, and writing the first encoded data into the first bank; and when second data is requested to be written into the second bank, reading the same reference data from the reference bank, and encoding the second data with the reference data to generate second encoded data, and writing the second encoded data into the second bank.

Abstract: A method for accessing a multi-port memory module comprising a plurality of banks is provided. In one embodiment, the method comprises: generating a plurality of parities, wherein each parity is generated according to bits of a portion of the banks; and writing the parities into the banks, respectively. In another embodiment, the method comprises: when two bits corresponding to two different addresses within a specific bank are requested to be read in response to two read commands, directly reading the bit corresponding to one of the two different address of the specific bank; and generating the bit corresponding to the other address of the specific bank by reading the bits of the other banks without the specific bank.

Abstract: A secure embedded system that uses cryptographic and biometric signal processing acceleration is described. In one embodiment, the secure embedded system is configured as a wireless pay-point protocol for brick-and-mortar and e-commerce applications in which biometric information is localized and does not require transmission of biometric data for authentication. In one embodiment, a key-generation function uses a dynamic key generator and static biometric components. In one embodiment, an embedded system design methodology provides hardware and software acceleration transparency.