Patents by Inventor Bo-Cheng Lai

Bo-Cheng Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12271383
    Abstract: The invention relates to a method and an apparatus for executing Structural Query Language (SQL) instructions in a Solid-state Storage Device (SSD). The apparatus includes: a processing unit; and a database accelerator. The processing unit is arranged operably to obtain an SQL query from a host side. The database accelerator is arranged operably to parse the SQL query according an SQL syntax tree to generate a series of table tasks to execute; and during the execution of the table tasks, read tables from a flash module through the processing unit, generate intermediate tables and sub-tables based on the read tables, and perform an arithmetic computation, a logical computation or both on a specific field in one intermediate table to generate a final dataset. The processing unit is arranged operably to reply to the host side with the final dataset.
    Type: Grant
    Filed: October 27, 2023
    Date of Patent: April 8, 2025
    Assignee: SILICON MOTION, INC.
    Inventors: Bo-Cheng Lai, Yen-Shi Kuo
  • Publication number: 20240152516
    Abstract: The invention relates to a method and an apparatus for executing Structural Query Language (SQL) instructions in a Solid-state Storage Device (SSD). The apparatus includes: a processing unit; and a database accelerator. The processing unit is arranged operably to obtain an SQL query from a host side. The database accelerator is arranged operably to parse the SQL query according an SQL syntax tree to generate a series of table tasks to execute; and during the execution of the table tasks, read tables from a flash module through the processing unit, generate intermediate tables and sub-tables based on the read tables, and perform an arithmetic computation, a logical computation or both on a specific field in one intermediate table to generate a final dataset. The processing unit is arranged operably to reply to the host side with the final dataset.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 9, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Bo-Cheng LAI, Yen-Shi KUO
  • Publication number: 20230122849
    Abstract: The present invention relates to a method of treating moderate or severe symptoms of COVID-19 using a plant composition. The plant composition comprises Prepared Monkshood Daughter Root (Aconitum carmichaelii), Fragrant Solomonseal Rhizome (Polygonatum odoratum), Indian Bread (Poria cocos), Pinellia tuber (Pinellia ternata), Oriental Wormwood Herb (Artemisia scoparia), Scutellaria Root (Scutellaria baicalensis), Mongolian Snakegourd Fruit (Trichosanthes kirilowii), Magnolia Bark (Magnolia officinalis), Heartleaf Houttuynia Herb (Houttuynia cordata), and Baked Licorice Root and Rhizome (Glycyrrhiza glabra), which is used as a traditional Chinese medicine composition.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 20, 2023
    Inventors: YI-CHANG SU, WEN-HUI CHIOU, YUH-CHIANG SHEN, WEN-CHI WEI, KENG-CHANG TSAI, CHIA-CHING LIAO, YU-HWEI TSENG, CHUN-TANG CHIOU, YU-CHI LIN, LI-HSIANG WANG, CHIEN-HSIEN HUANG, CHIA-MO LIN, CHI-KUEI LIN, YI-CHIA HUANG, CHIEN-JUNG LIN, JUI-SHAN LIN, YA-SUNG YANG, CHUN-HSIANG CHIU, SHUN-PING CHENG, HSIEN-HWA KUO, WU-PU LIN, CHEN-SHIEN LIN, BO-CHENG LAI, YUAN-NIAN HSU, TSUNG-LUNG TSAI, WEI-CHEN HSU, TIENG-SIONG FONG, YI-WEN HUANG, CHIA-I TSAI, YA-CHEN YANG, MING-CHE TSAI, MING-HUEI CHENG, SHIH-WEI HUANG
  • Publication number: 20180330235
    Abstract: An apparatus includes a memory unit configured to store nonzero entries of a first array and nonzero entries of a second array based on a sparse matrix format; and an index module configured to select the common nonzero entries of the neurons and the corresponding weights. Since the values of the nonzero entries of the neurons and corresponding weights are selected and accessed, the data load and movement from the memory unit can be reduced to save power consumption. In addition, for a sparse neuronal network model with a large scale, through the operations of the index module, the computation regarding a great amount of zero entries can be scattered to improve overall computation speed of a neural network.
    Type: Application
    Filed: May 15, 2017
    Publication date: November 15, 2018
    Inventors: Chien-Yu Lin, Bo-Cheng Lai
  • Patent number: 9973214
    Abstract: A low density parity check (LDPC) decoding method and a decoding apparatus are provided. The method includes following steps. Based on M edges of a Tanner graph related to a parity check matrix, each of the edges is associated with one of a plurality of threads, such that each of the threads is corresponding to one of a plurality of edge identifies. When executing one of the threads, data in a shared memory is accessed according to the edge identifier of the one of the threads, so as to update a plurality of passing massages respectively corresponding to the edges in the shared memory. Thereby, high computation parallelism and fully-coalesced data accesses can be achieved.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 15, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Bo-Cheng Lai, Tsou-Han Chiu
  • Publication number: 20170012643
    Abstract: A low density parity check (LDPC) decoding method and a decoding apparatus are provided. The method includes following steps. Based on M edges of a Tanner graph related to a parity check matrix, each of the edges is associated with one of a plurality of threads, such that each of the threads is corresponding to one of a plurality of edge identifies. When executing one of the threads, data in a shared memory is accessed according to the edge identifier of the one of the threads, so as to update a plurality of passing massages respectively corresponding to the edges in the shared memory. Thereby, high computation parallelism and fully-coalesced data accesses can be achieved.
    Type: Application
    Filed: July 7, 2016
    Publication date: January 12, 2017
    Inventors: Bo-Cheng Lai, Tsou-Han Chiu
  • Publication number: 20160313923
    Abstract: A method for accessing a multi-port memory module comprising a plurality of banks is provided. In one embodiment, the method comprises: generating a plurality of parities, wherein each parity is generated according to bits of a portion of the banks; and writing the parities into the banks, respectively. In another embodiment, the method comprises: when two bits corresponding to two different addresses within a specific bank are requested to be read in response to two read commands, directly reading the bit corresponding to one of the two different address of the specific bank; and generating the bit corresponding to the other address of the specific bank by reading the bits of the other banks without the specific bank.
    Type: Application
    Filed: April 14, 2016
    Publication date: October 27, 2016
    Inventors: Bo-Cheng Lai, Jiun-Liang Lin, Kuo-Cheng Lu
  • Publication number: 20160314821
    Abstract: A method for accessing a multi-port memory module comprising a plurality of banks is provided, wherein the plurality of banks comprise at least a first bank, a second bank and a reference bank, and the method comprises: when first data is requested to be written into the first bank, reading reference data from the reference bank, and encoding the first data with the reference data to generate first encoded data, and writing the first encoded data into the first bank; and when second data is requested to be written into the second bank, reading the same reference data from the reference bank, and encoding the second data with the reference data to generate second encoded data, and writing the second encoded data into the second bank.
    Type: Application
    Filed: April 14, 2016
    Publication date: October 27, 2016
    Inventors: Kuo-Cheng Lu, Bo-Cheng Lai, Kun-Hua Huang, Jiun-Liang Lin
  • Publication number: 20070038867
    Abstract: A secure embedded system that uses cryptographic and biometric signal processing acceleration is described. In one embodiment, the secure embedded system is configured as a wireless pay-point protocol for brick-and-mortar and e-commerce applications in which biometric information is localized and does not require transmission of biometric data for authentication. In one embodiment, a key-generation function uses a dynamic key generator and static biometric components. In one embodiment, an embedded system design methodology provides hardware and software acceleration transparency.
    Type: Application
    Filed: June 2, 2004
    Publication date: February 15, 2007
    Inventors: Ingrid Verbauwhede, Patrick Schaumont, David Hwang, Bo-Cheng Lai, Shenglin Yang, Kazuo Sakiyama, Yi Fan, Alireza Hodjat