Patents by Inventor Bo Chu

Bo Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12259371
    Abstract: Carrier gas connection devices (100, 402, 404, 406, 408) enable one to change the carrier gas provided to a gas chromatography channel. The carrier gas connection devices (100, 402, 404, 406, 408) comprise a channel adaptor (102, 202), a carrier block (104, 302), and a clamping system, and two or more channel adaptor positions. In each of the channel adaptor positions, a fluid-tight flow path for carrier gas out of the carrier block (104,302) into the channel adaptor (102, 202) is formed. Carrier gas distribution systems (400), gas chromatography instruments, and methods of changing a carrier gas supplied to a GC are also provided.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 25, 2025
    Assignee: Agilent Technologies, Inc.
    Inventor: Bo Chu
  • Publication number: 20240221255
    Abstract: This application provides techniques for generating customized prop images. The techniques comprise obtaining an initial prop image that comprises a target object, wherein the initial prop image comprises an initial image of any prop among at least one prop held by a target online streamer; obtaining an action file configured to specify an action of the target object; parsing the action file to determine a target action corresponding to the action file; and generating a customized prop image by updating a current action of the target object in the initial prop image to the target action, wherein the customized prop image corresponds to the target online streamer.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 4, 2024
    Inventors: Zhicheng NA, Bo CHU
  • Publication number: 20240060761
    Abstract: An efficient and energy-saving blasting method based on a notched blast hole includes forming a cutting hole, an auxiliary hole, and a peripheral hole on a surface of an area to be blasted separately by means of a drilling apparatus. The cutting hole, the auxiliary hole, and the peripheral hole are formed on the surface of the blasting area separately, and notches with different numbers are formed on outer sides of the holes separately, such that in a blasting process, explosion energy of explosives can be transmitted along the notches, the explosion energy is guided, energy loss is reduced, blasting efficiency is improved, thus a range of a crushing area is reduced, a length of a main crack is increased, and a better blasting effect is achieved. Moreover, explosive energy is concentrated on the notch to initiate crack, so as to reduce an explosion smash area.
    Type: Application
    Filed: July 13, 2023
    Publication date: February 22, 2024
    Applicant: Chongqing Jiaotong University
    Inventors: Xuefu ZHANG, Bo HU, Jian ZHANG, Bo CHU, Chunlong WANG, Peiheng GUO, Qiusheng DENG
  • Publication number: 20220011279
    Abstract: Carrier gas connection devices (100, 402, 404, 406, 408) enable one to change the carrier gas provided to a gas chromatography channel. The carrier gas connection devices (100, 402, 404, 406, 408) comprise a channel adaptor (102, 202), a carrier block (104, 302), and a clamping system, and two or more channel adaptor positions. In each of the channel adaptor positions, a fluid-tight flow path for carrier gas out of the carrier block (104,302) into the channel adaptor (102, 202) is formed. Carrier gas distribution systems (400), gas chromatography instruments, and methods of changing a carrier gas supplied to a GC are also provided.
    Type: Application
    Filed: November 16, 2018
    Publication date: January 13, 2022
    Inventor: Bo CHU
  • Patent number: 8039844
    Abstract: This invention provides a top-gate microcrystalline thin film transistor and a method for manufacturing the same. An inversion layer channel is formed in a top interface of a microcrystalline active layer, and being separated from an incubation layer in a bottom interface of the microcrystalline active layer. The inversion layer channel is formed in the crystallized layer of the top interface of the microcrystalline active layer. As such, the present microcrystalline thin film transistor has better electrical performance and reliability.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: October 18, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Ju Tsai, Bo-Chu Chen, Ding-Kang Shih, Jung-Jie Huang, Yung-Hui Yeh
  • Publication number: 20090184321
    Abstract: This invention provides a top-gate microcrystalline thin film transistor and a method for manufacturing the same. An inversion layer channel is formed in a top interface of a microcrystalline active layer, and being separated from an incubation layer in a bottom interface of the microcrystalline active layer. The inversion layer channel is formed in the crystallized layer of the top interface of the microcrystalline active layer. As such, the present microcrystalline thin film transistor has better electrical performance and reliability.
    Type: Application
    Filed: August 12, 2008
    Publication date: July 23, 2009
    Inventors: Cheng-Ju TSAI, Bo-Chu CHEN, Ding-Kang SHIH, Jung-Jie HUANG, Yung-Hui YEH
  • Publication number: 20090179842
    Abstract: A flat display panel is provided. The flat display panel includes a plurality of scan lines, a plurality of data lines, and a plurality of pixels arranged in an (m×n) array, in which both m and n are integers greater than 2. Each of the pixels includes four sub-pixels arranged in a (2×2) array. In each of the pixels, the sub-pixels are connected with one of the scan lines and one of the data lines correspondingly, and display different color lights, respectively. In any four pixels arranged in a (2×2) array, the four sub-pixels located at the center area display the same color light.
    Type: Application
    Filed: September 3, 2008
    Publication date: July 16, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Bo-Chu Chen, King-Yuan Ho, Yung-Hui Yeh
  • Patent number: 7495736
    Abstract: A pixel array with flexible circuit layout is disclosed, which comprises: a substrate, having a first surface; a plurality of scan lines; and a plurality of data lines; wherein the plural scan lines are disposed on the first surface while each has a profile defined by a non-linear first function, and the plural data lines are disposed on the first surface while each has a profile defined by a non-linear second function. When the pixel array is adapted for a flexible display and the display is being bended, the flexible circuit layout of the pixel array of the invention can effectively reduce the risk of the snapping of the conductive wires used in the pixel array so that the flexibility and reliability of the flexible display are enhanced.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: February 24, 2009
    Assignee: Industrial Technology Research Instituti
    Inventors: Bo-Chu Chen, Huai-Yuan Tseng, Yung-Hui Yeh, Ching-Chieh Lin
  • Publication number: 20070019143
    Abstract: A pixel array with flexible circuit layout is disclosed, which comprises: a substrate, having a first surface; a plurality of scan lines; and a plurality of data lines; wherein the plural scan lines are disposed on the first surface while each has a profile defined by a non-linear first function, and the plural data lines are disposed on the first surface while each has a profile defined by a non-linear second function. When the pixel array is adapted for a flexible display and the display is being bended, the flexible circuit layout of the pixel array of the invention can effectively reduce the risk of the snapping of the conductive wires used in the pixel array so that the flexibility and reliability of the flexible display are enhanced.
    Type: Application
    Filed: August 31, 2005
    Publication date: January 25, 2007
    Inventors: Bo-Chu Chen, Huai-Yuan Tseng, Yung-Hui Yeh, Ching-Chieh Lin
  • Publication number: 20070001202
    Abstract: A structure having a dielectric layer sandwiched between two conductors for providing enhanced cracking resistance to the dielectric layer is disclosed, which comprises a bottom electrode layer, a dielectric layer and a top electrode layer. The structure of the invention is designed with a specific layout that prevents the dielectric layer from cracking while it is formed on a flexible substrate and is subjected to a stress developed by the bending of the substrate. The structure of invention not only can enhance the reliability of an electronic component implementing the structure, but also increase the flexibility of the dielectric layer.
    Type: Application
    Filed: July 29, 2005
    Publication date: January 4, 2007
    Inventors: Huai-Yuan Tseng, Bo-Chu Chen, Ching-Chieh Lin
  • Patent number: D884524
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: May 19, 2020
    Assignee: Agilent Technologies, Inc.
    Inventors: Bo Chu, Fanny Hauser, Cathrin Sohns, Qi Siegmundt-Pan
  • Patent number: D1039404
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: August 20, 2024
    Assignee: THERMO FISHER SCIENTIFIC (SHANGHAI) INSTRUMENTS CO., LTD.
    Inventors: Beng Heng Lim, Bo Chu