Abstract: This invention provides a top-gate microcrystalline thin film transistor and a method for manufacturing the same. An inversion layer channel is formed in a top interface of a microcrystalline active layer, and being separated from an incubation layer in a bottom interface of the microcrystalline active layer. The inversion layer channel is formed in the crystallized layer of the top interface of the microcrystalline active layer. As such, the present microcrystalline thin film transistor has better electrical performance and reliability.

Abstract: This invention provides a top-gate microcrystalline thin film transistor and a method for manufacturing the same. An inversion layer channel is formed in a top interface of a microcrystalline active layer, and being separated from an incubation layer in a bottom interface of the microcrystalline active layer. The inversion layer channel is formed in the crystallized layer of the top interface of the microcrystalline active layer. As such, the present microcrystalline thin film transistor has better electrical performance and reliability.

Abstract: A flat display panel is provided. The flat display panel includes a plurality of scan lines, a plurality of data lines, and a plurality of pixels arranged in an (m×n) array, in which both m and n are integers greater than 2. Each of the pixels includes four sub-pixels arranged in a (2×2) array. In each of the pixels, the sub-pixels are connected with one of the scan lines and one of the data lines correspondingly, and display different color lights, respectively. In any four pixels arranged in a (2×2) array, the four sub-pixels located at the center area display the same color light.

Abstract: A pixel array with flexible circuit layout is disclosed, which comprises: a substrate, having a first surface; a plurality of scan lines; and a plurality of data lines; wherein the plural scan lines are disposed on the first surface while each has a profile defined by a non-linear first function, and the plural data lines are disposed on the first surface while each has a profile defined by a non-linear second function. When the pixel array is adapted for a flexible display and the display is being bended, the flexible circuit layout of the pixel array of the invention can effectively reduce the risk of the snapping of the conductive wires used in the pixel array so that the flexibility and reliability of the flexible display are enhanced.

Abstract: A pixel array with flexible circuit layout is disclosed, which comprises: a substrate, having a first surface; a plurality of scan lines; and a plurality of data lines; wherein the plural scan lines are disposed on the first surface while each has a profile defined by a non-linear first function, and the plural data lines are disposed on the first surface while each has a profile defined by a non-linear second function. When the pixel array is adapted for a flexible display and the display is being bended, the flexible circuit layout of the pixel array of the invention can effectively reduce the risk of the snapping of the conductive wires used in the pixel array so that the flexibility and reliability of the flexible display are enhanced.

Abstract: A structure having a dielectric layer sandwiched between two conductors for providing enhanced cracking resistance to the dielectric layer is disclosed, which comprises a bottom electrode layer, a dielectric layer and a top electrode layer. The structure of the invention is designed with a specific layout that prevents the dielectric layer from cracking while it is formed on a flexible substrate and is subjected to a stress developed by the bending of the substrate. The structure of invention not only can enhance the reliability of an electronic component implementing the structure, but also increase the flexibility of the dielectric layer.