Patents by Inventor Bo-Cyuan Lu
Bo-Cyuan Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200035814Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a fin extending above an isolation region. A sacrificial gate is formed over the fin. A first dielectric material is selectively deposited on sidewalls of the sacrificial gate to form spacers on the sidewalls of the sacrificial gate. The fin is patterned using the sacrificial gate and the spacers as a combined mask to form a recess in the fin. An epitaxial source/drain region is formed in the recess.Type: ApplicationFiled: October 4, 2019Publication date: January 30, 2020Inventors: Chung-Ting Ko, Bo-Cyuan Lu, Jr-Hung Li, Chi On Chui
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Patent number: 10535569Abstract: A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.Type: GrantFiled: July 30, 2018Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Bo-Yu Lai, Bo-Cyuan Lu, Chi On Chui, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 10510612Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.Type: GrantFiled: November 29, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Cyuan Lu, Chunyao Wang, Jr-Hung Li, Chung-Ting Ko, Chi On Chui
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Patent number: 10504990Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.Type: GrantFiled: February 27, 2018Date of Patent: December 10, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Wen Wu, Fu-Kai Yang, Chen-Ming Lee, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
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Patent number: 10505021Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a fin extending above an isolation region. A sacrificial gate is formed over the fin. A first dielectric material is selectively deposited on sidewalls of the sacrificial gate to form spacers on the sidewalls of the sacrificial gate. The fin is patterned using the sacrificial gate and the spacers as a combined mask to form a recess in the fin. An epitaxial source/drain region is formed in the recess.Type: GrantFiled: February 28, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ting Ko, Bo-Cyuan Lu, Jr-Hung Li, Chi On Chui
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Patent number: 10483168Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.Type: GrantFiled: December 6, 2017Date of Patent: November 19, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Cyuan Lu, Chunyao Wang, Jr-Hung Li, Chung-Ting Ko, Chi On Chui
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Patent number: 10475788Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a first gate structure formed over the fin structure. The FinFET device structure also includes a first capping layer formed over the first gate structure and a first etching stop layer over the first capping layer and the first gate structure. The FinFET device structure further includes a first source/drain (S/D) contact structure formed over the fin structure and adjacent to the first gate structure. A portion of the first etching stop layer which is directly above the first capping layer is higher than another portion of the first etching stop layer which is directly above the first gate spacer layer.Type: GrantFiled: November 24, 2017Date of Patent: November 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
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Publication number: 20190341476Abstract: A method includes depositing an inhibitor layer on a first surface, depositing a film on a second surface by performing a first set of deposition cycles. Each deposition cycle includes adsorbing a first precursor over the second surface, performing a first purge process, adsorbing a second precursor over the second surface, and performing a second purge process. The method also includes performing a third purge process that is different from the first purge process or the second purge process.Type: ApplicationFiled: July 15, 2019Publication date: November 7, 2019Inventors: Chi On Chui, Bo-Cyuan Lu
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Patent number: 10468529Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a gate structure over the substrate and having a sidewall, a spacer element over the sidewall of the gate structure and a source/drain portion adjacent to the spacer element and the gate structure. The semiconductor device structure also includes an etch stop layer over the source/drain portion, an interlayer dielectric layer over the etch stop layer and in contact with the spacer element, and a contact plug penetrating through the interlayer dielectric layer and the etch stop layer, and electrically connected to the source/drain portion.Type: GrantFiled: July 11, 2017Date of Patent: November 5, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ting Ko, Bo-Cyuan Lu, Jr-Hung Li, Chi-On Chui
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Patent number: 10355111Abstract: A method includes depositing an inhibitor layer on a first surface, depositing a film on a second surface by performing a first set of deposition cycles. Each deposition cycle includes adsorbing a first precursor over the second surface, performing a first purge process, adsorbing a second precursor over the second surface, and performing a second purge process. The method also includes performing a third purge process that is different from the first purge process or the second purge process.Type: GrantFiled: September 1, 2017Date of Patent: July 16, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi On Chui, Bo-Cyuan Lu
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Publication number: 20190181247Abstract: A method of manufacturing a semiconductor device comprises forming a spacer material on the semiconductor fin and the gate stack, wherein the forming the spacer material further comprises using atomic layer deposition to deposit a first material on the semiconductor fin and using atomic layer deposition to deposit a second material on the first material, wherein the second material is different from the first material. The spacer material is removed from the semiconductor fin, wherein the removing the spacer material further comprises implanting an etching modifier into the spacer material to form a modified spacer material and removing the modified spacer material.Type: ApplicationFiled: February 18, 2019Publication date: June 13, 2019Inventors: Bo-Cyuan Lu, Tai-Chun Huang
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Publication number: 20190164960Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a first gate structure formed over the fin structure. The FinFET device structure also includes a first capping layer formed over the first gate structure and a first etching stop layer over the first capping layer and the first gate structure. The FinFET device structure further includes a first source/drain (S/D) contact structure formed over the fin structure and adjacent to the first gate structure. A portion of the first etching stop layer which is directly above the first capping layer is higher than another portion of the first etching stop layer which is directly above the first gate spacer layer.Type: ApplicationFiled: November 24, 2017Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Han CHEN, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG, Jr-Hung LI, Bo-Cyuan LU
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Publication number: 20190157387Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.Type: ApplicationFiled: February 27, 2018Publication date: May 23, 2019Inventors: I-Wen Wu, Fu-Kai Yang, Chen-Ming Lee, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
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Publication number: 20190148239Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.Type: ApplicationFiled: November 29, 2018Publication date: May 16, 2019Inventors: Bo-Cyuan Lu, Chunyao Wang, Jr-Hung Li, Chung-Ting Ko, Chi On Chui
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Publication number: 20190148238Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.Type: ApplicationFiled: December 6, 2017Publication date: May 16, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Cyuan LU, Chunyao WANG, Jr-Hung LI, Chung-Ting KO, Chi On Chui
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Publication number: 20190131421Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.Type: ApplicationFiled: October 30, 2017Publication date: May 2, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Huang-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
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Publication number: 20190103477Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a fin extending above an isolation region. A sacrificial gate is formed over the fin. A first dielectric material is selectively deposited on sidewalls of the sacrificial gate to form spacers on the sidewalls of the sacrificial gate. The fin is patterned using the sacrificial gate and the spacers as a combined mask to form a recess in the fin. An epitaxial source/drain region is formed in the recess.Type: ApplicationFiled: February 28, 2018Publication date: April 4, 2019Inventors: Chung-Ting Ko, Bo-Cyuan Lu, Jr-Hung Li, Chi On Chui
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Patent number: 10211318Abstract: A method of manufacturing a semiconductor device comprises forming a spacer material on the semiconductor fin and the gate stack, wherein the forming the spacer material further comprises using atomic layer deposition to deposit a first material on the semiconductor fin and using atomic layer deposition to deposit a second material on the first material, wherein the second material is different from the first material. The spacer material is removed from the semiconductor fin, wherein the removing the spacer material further comprises implanting an etching modifier into the spacer material to form a modified spacer material and removing the modified spacer material.Type: GrantFiled: January 12, 2017Date of Patent: February 19, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-Cyuan Lu, Tai-Chun Huang
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Publication number: 20190019890Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a gate structure over the substrate and having a sidewall, a spacer element over the sidewall of the gate structure and a source/drain portion adjacent to the spacer element and the gate structure. The semiconductor device structure also includes an etch stop layer over the source/drain portion, an interlayer dielectric layer over the etch stop layer and in contact with the spacer element, and a contact plug penetrating through the interlayer dielectric layer and the etch stop layer, and electrically connected to the source/drain portion.Type: ApplicationFiled: July 11, 2017Publication date: January 17, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ting KO, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI
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Publication number: 20180337100Abstract: A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.Type: ApplicationFiled: July 30, 2018Publication date: November 22, 2018Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Bo-Yu Lai, Bo-Cyuan Lu, Chi On Chui, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen