Patents by Inventor Bo-Feng YOUNG

Bo-Feng YOUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210126099
    Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a bottom dielectric layer, and a gate stack. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The bottom dielectric layer is disposed between the at least one fin and the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets.
    Type: Application
    Filed: February 24, 2020
    Publication date: April 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi-On Chui
  • Publication number: 20210091228
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first negative capacitance material over a substrate and patterning the first negative capacitance material to form a fin structure over the substrate. The method also includes forming a source feature and a drain feature in and protruding from a source region and a drain region of the fin structure. The method also includes forming a gate dielectric structure between the source feature and the drain feature to cover a channel region of the fin structure and forming a gate electrode layer over the gate dielectric structure.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng YOUNG, Chih-Yu CHANG, Sai-Hooi YEONG, Chi-On CHUI, Chih-Hao WANG
  • Publication number: 20210043751
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sai-Hooi YEONG, Chi-On CHUI, Bo-Feng YOUNG, Bo-Yu LAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20210036128
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.
    Type: Application
    Filed: October 8, 2020
    Publication date: February 4, 2021
    Inventors: Bo-Feng Young, Che-Cheng Chang, Mu-Tsang Lin, Tung-Wen Cheng, Zhe-Hao Zhang
  • Publication number: 20210035870
    Abstract: A semiconductor device is provided. The device includes a first pair and a second pair of source/drain features over a semiconductor substrate. The first pair of source/drain features are p-type doped. The second pair of source/drain features are n-type doped. A first stack of semiconductor layers connect the first pair of source/drain features along a first direction. A second stack of semiconductor layers connect the second pair of source/drain features along a second direction. A first gate is between vertically adjacent layers of the first stack of semiconductor layers. The first gate has a first portion that has a first dimension along the first direction. A second gate is between vertically adjacent layers of the second stack of semiconductor layers. The second gate has a second portion that has a second dimension along the second direction. The second dimension is larger than the first dimension.
    Type: Application
    Filed: May 15, 2020
    Publication date: February 4, 2021
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20210020786
    Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming LIN, Sai-Hooi YEONG, Ziwei FANG, Bo-Feng YOUNG, Chi On CHUI, Chih-Yu CHANG, Huang-Lin CHAO
  • Patent number: 10861968
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure that includes a negative capacitance (NC) material. The semiconductor device structure also includes a gate electrode layer, a gate dielectric structure, a source feature, and a drain feature. The gate dielectric structure covers the top surface and the opposing sidewall surfaces of the fin structure. The gate electrode layer is formed over the gate dielectric structure. The source feature and the drain feature are formed in and protrude from the fin structure, and separated from each other by the gate electrode layer.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Feng Young, Chih-Yu Chang, Sai-Hooi Yeong, Chi-On Chui, Chih-Hao Wang
  • Publication number: 20200381559
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure that includes a negative capacitance (NC) material. The semiconductor device structure also includes a gate electrode layer, a gate dielectric structure, a source feature, and a drain feature. The gate dielectric structure covers the top surface and the opposing sidewall surfaces of the fin structure. The gate electrode layer is formed over the gate dielectric structure. The source feature and the drain feature are formed in and protrude from the fin structure, and separated from each other by the gate electrode layer.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Feng YOUNG, Chih-Yu CHANG, Sai-Hooi YEONG, Chi-On CHUI, Chih-Hao WANG
  • Patent number: 10854519
    Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure, the virtual surface is formed between the upper portion and the lower portion, and the lower portion has a tapered width which is gradually tapered from the virtual interface to a bottom surface of the lower portion.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Bo-Feng Young, Yi-Jen Chen
  • Publication number: 20200357655
    Abstract: A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.
    Type: Application
    Filed: July 30, 2020
    Publication date: November 12, 2020
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Chia-Yang Liao, Bo-Feng Young
  • Patent number: 10833167
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: November 10, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Chi-On Chui, Bo-Feng Young, Bo-Yu Lai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10811516
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Che-Cheng Chang, Mu-Tsang Lin, Tung-Wen Cheng, Zhe-Hao Zhang
  • Publication number: 20200273969
    Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Bo-Feng Young, Che-Cheng Chang, Po-Chi Wu
  • Patent number: 10741408
    Abstract: A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Chia-Yang Liao, Bo-Feng Young
  • Publication number: 20200176585
    Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.
    Type: Application
    Filed: October 8, 2019
    Publication date: June 4, 2020
    Inventors: Bo-Feng Young, Chih-Yu Chang, Sai-Hooi Yeong, Chi On Chui, Chih-Hao Wang
  • Patent number: 10665700
    Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Che-Cheng Chang, Po-Chi Wu
  • Publication number: 20200135883
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.
    Type: Application
    Filed: January 25, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sai-Hooi YEONG, Chi-On CHUI, Bo-Feng YOUNG, Bo-Yu LAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20200035832
    Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.
    Type: Application
    Filed: October 7, 2019
    Publication date: January 30, 2020
    Inventors: Cheng-Yen YU, Che-Cheng CHANG, Tung-Wen CHENG, Zhe-Hao ZHANG, Bo-Feng YOUNG
  • Patent number: 10483394
    Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
  • Publication number: 20190252529
    Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Bo-Feng Young, Che-Cheng Chang, Po-Chi Wu