Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Systems and methods are provided for reading data from non-volatile storage devices and decoding the read data. A method may include obtaining a unique identifier for a storage location to be read, retrieving from a memory an adjustment to read reference voltage (Vref) associated with the unique identifier, performing a read operation on the storage location using a read reference voltage adjusted by the adjustment to Vref, decoding data read from the storage location in a decoding process and updating the adjustment to Vref with decoding information generated during the decoding process.

Abstract: A semiconductor device includes a first semiconductor die having a top planar surface and a second semiconductor die having a bottom planar surface and a top planar surface. A protective layer including a bottom planar surface and a top planar surface is positioned between the first semiconductor die and the second semiconductor die. An adhesive layer having a top planar surface and a bottom planar surface is between the protective layer and the second semiconductor die. A periphery of the top planar surface of the first semiconductor die is covered by a periphery of the bottom planar surface of the protective layer after cutting a portion of the protective layer that extended past the periphery of the surface of the first semiconductor die. The protective layer reduces the occurrence of peeling of the second semiconductor die and first semiconductor die coupled to the protective layer.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: A fan includes a housing, a rotation body, and an auxiliary inlet. The housing includes an accommodation chamber, an air inlet, and an air outlet. The rotation body is arranged in the accommodation chamber, forms a guide channel with an inner wall of the accommodation chamber, and is configured to drive air to enter from the air inlet and be guided out from the air outlet through the guide channel. The auxiliary inlet is arranged on the guide channel and configured to introduce the air into the guide channel.

Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method may comprise receiving a chunk of data read from a physical location of a non-volatile storage device and searching a memory for soft information associated with the physical location using a unique identifier associated with the physical location. The soft information may be generated from one or more previous decoding processes on previous data from the physical location. The method may further comprise retrieving the soft information identified by the unique identifier associated with the physical location from the memory, decoding the chunk of data with the soft information indicating reliability of bits in the chunk of data and updating the soft information with decoding information generated during the decoding.

Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

Abstract: Systems and methods are provided for reading data from non-volatile storage devices and decoding the read data. A method may include obtaining a unique identifier for a storage location to be read, retrieving from a memory an adjustment to read reference voltage (Vref) associated with the unique identifier, performing a read operation on the storage location using a read reference voltage adjusted by the adjustment to Vref, decoding data read from the storage location in a decoding process and updating the adjustment to Vref with decoding information generated during the decoding process.

Abstract: Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.

Abstract: A heart rate module, comprising a housing structure composed of a rear housing (2) and a light-transmitting cover plate (3), the housing structure being internally provided with a PCB assembly (1); the PCB assembly (1) comprises a PCB, PDs (6, 7) and an LED (5), the PDs (6, 7) and the LED (5) being fixed on the PCB according to a preset distance; a hot melt positioning column (21) is provided on the rear housing (2), and the PCB assembly (1) is fixed, by means of the hot melt positioning column (21), on the rear housing (2). Use of the heart rate module can solve the problems of the assembly method of the available heart rate meter being complicated and the requirement for a terminal product being high.

Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

Abstract: A method of detecting a back of a shelf for supporting objects includes: obtaining an image depicting a shelf having a shelf edge and a support surface extending from the shelf edge to a shelf back; decomposing the image into a plurality of patches; for each patch: generating a feature descriptor; based on the feature descriptor, assigning one of a shelf back classification and a non-shelf back classification to the patch; generating a mask corresponding to the image, the mask containing an indication of the classification assigned to each of the patches; and presenting the mask.

Abstract: A method for publishing a smart contract includes: generating a version number index value according to a contract name of the smart contract, and searching for an associated target contract version number from a blockchain network according to the version number index value; generating a contract index value according to a contract version number of the smart contract and the contract name, in response to determining that the contract version number of the smart contract is greater than the target contract version number; associating the contract index value with the smart contract and associating the version number index value with the contract version number of the smart contract, to generate transaction information; and publishing the transaction information to the blockchain network, to publish the smart contract to the blockchain network.

Abstract: Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.

Abstract: A temperature control system and a driving method thereof, and a liquid crystal apparatus are provided.

Abstract: Systems, apparatus and methods are provided for using a partial logical-to-physical (L2P) address translation table for multiple namespaces to perform address translation. An exemplary embodiment may provide a method comprising: receiving a request for a first logical data address (LDA) that belongs to a first namespace (NS); searching the first NS in an entry location table (ELT) for all namespaces whose L2P entries always reside in memory; determining that the first NS is not in the ELT; searching a cache of lookup directory entries of recently accessed translation data units (TDUs) for a first TDU containing a L2P entry for the first LDA; determining that there is a cache miss; retrieving the lookup directory entry for the first TDU from an in-memory lookup directory and determining that it is not valid; reserving a TDU space for the first TDU; and generating a load request for the first TDU.

Abstract: Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.

Abstract: To solve the problem of large electromagnetic noise in AC traction motor, embodiments have open square notches at symmetrical positions on both sides of stator teeth of AC traction motor to effectively reduce electromagnetic noise without affecting other performance indicators of motor. In addition, embodiments fit the functional relationship between the optimal notch size or optimal slotting position size of motors and their power by determining the optimal notch size or optimal slotting position size of motors with different power grades, so as to achieve the noise reduction effect.

Abstract: Systems, apparatus and methods are provided for using a partial logical-to-physical (L2P) address translation table for multiple namespaces to perform address translation. An exemplary embodiment may provide a method comprising: receiving a request for a first logical data address (LDA) that belongs to a first namespace (NS); searching the first NS in an entry location table (ELT) for all namespaces whose L2P entries always reside in memory; determining that the first NS is not in the ELT; searching a cache of lookup directory entries of recently accessed translation data units (TDUs) for a first TDU containing a L2P entry for the first LDA; determining that there is a cache miss; retrieving the lookup directory entry for the first TDU from an in-memory lookup directory and determining that it is not valid; reserving a TDU space for the first TDU; and generating a load request for the first TDU.