Patents by Inventor Bo-Han Chen
Bo-Han Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240110875Abstract: A coherent Raman spectro-microscopy system is configured for generating a spectro-microscopic image of a sample and includes a light source, a supercontinuum spectrum generator, a color filter assembly, and a spectro-microscopic assembly. The light source is for emitting at least one pulsed laser beam. The supercontinuum spectrum generator is for broadening the bandwidth of at least one pulsed laser beam. The color filter assembly is for filtering the bandwidth of at least one pulsed laser beam according to a predetermined bandwidth and converting at least one pulsed laser beam into a coherent spectro-microscopic laser beam. The sample is disposed in the spectro-microscopic assembly, and the spectro-microscopic assembly receives the coherent spectro-microscopic laser beam so that the coherent spectro-microscopic laser beam passes through the sample to generate the spectro-microscopic image of the sample.Type: ApplicationFiled: January 18, 2023Publication date: April 4, 2024Inventors: Shang-Da YANG, Chih-Hsuan Lu, Bo-Han Chen
-
Publication number: 20240111849Abstract: A media docking device includes an input circuit, an output circuit and a processing circuit. The input circuit is electrically connected to a media source device for receiving media data. The output circuit is electrically connected to a media play device. The processing circuit is electrically connected to the input circuit and the output circuit. The processing circuit determines if a verification procedure is passed. If the verification procedure is passed, the processing circuit transfers the media data to the media play device. If the verification procedure is not passed, the processing circuit limits a transmission of the media data, such that the media data will not be completely played by the media play device.Type: ApplicationFiled: October 4, 2023Publication date: April 4, 2024Inventors: Chien-Wei CHEN, Tsung-Han LI, You-Wen CHIOU, Kuan-Chi CHOU, Bo Yu LAI
-
Publication number: 20240114207Abstract: A media docking device includes an input module, an output module and a processing module. The input module is electrically connected to a media source device for receiving media data. The output module is electrically connected to a media play device. The processing module determines if an instruction is received from the media source device or a remote device. If the instruction is not received, the processing module transfers the media data to the output module to transmit to the media play device. If the instruction is received, the processing module limits a transmission of the media data according to the instruction, such that the media data will not be completely played by the media play device.Type: ApplicationFiled: October 4, 2023Publication date: April 4, 2024Inventors: Chien-Wei CHEN, Tsung-Han LI, You-Wen CHIOU, Kuan-Chi CHOU, Bo Yu LAI
-
Publication number: 20240066635Abstract: A laser machining device includes a pulsed laser generator, an accommodation chamber, a bandwidth broadening unit and a pulse compression unit. The pulsed laser generator is configured to emit a pulsed laser. The accommodation chamber has a gas inlet. The bandwidth broadening unit is disposed in the accommodation chamber, and is configured to broaden a frequency bandwidth of the pulsed laser to obtain a broad bandwidth pulsed laser. The pulse compression unit is disposed in the accommodation chamber. The bandwidth broadening unit and the pulse compression unit are arranged in order along a laser propagation path, and the pulse compression unit is configured to compress a pulse duration of the broad bandwidth pulsed laser.Type: ApplicationFiled: October 5, 2022Publication date: February 29, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yi-Chi LEE, Bo-Han CHEN, Chih-Hsuan LU, Ping-Han WU, Zih-Yi LI, Shang-Yu HSU
-
Patent number: 11916155Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.Type: GrantFiled: May 21, 2021Date of Patent: February 27, 2024Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATIONInventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
-
Patent number: 11748549Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.Type: GrantFiled: April 21, 2021Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien-Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
-
Publication number: 20230175077Abstract: Provided is a diagnostic system for identifying target microorganisms and/or resistance genes in a sample, including a cell lysis unit, a target nucleic acid enriching unit, a sequencing unit, and a sequence analyzing unit, wherein the cell lysis unit is configured to lyse non-target cells in the sample, the target nucleic acid enriching unit equipped with an immobilized adsorption device is configured to deplete nucleic acids of the non-target cells and to enrich nucleic acids of the target microorganisms, and the sequencing unit and the sequence analyzing unit are configured to produce identification results of the microbial species and/or resistance genes from the sequences of the enriched nucleic acids. Also provided is a method for enriching target nucleic acids in a sample and a method for identifying target microorganisms and/or resistance genes by sequencing the enriched nucleic acids of the target microorganisms.Type: ApplicationFiled: December 6, 2022Publication date: June 8, 2023Applicant: CENTERS FOR DISEASE CONTROL, MINISTRY OF HEALTH AND WELFAREInventors: Chien-Shun CHIOU, Hui-Yung SONG, Bo-Han CHEN, Yu-Ping HONG, Min-Chi LU, Hui-Ling TANG
-
Publication number: 20230042170Abstract: A biological hair shape change composition including a macromolecular component, a small molecular component and an alkali agent component is provided. The macromolecular component includes a protease belonging to the class of alkaline proteases, and the small molecular component includes a peptide with reduction activity. Both the macromolecular component and the small molecular component are obtained from a fermentation product of Bacillus licheniformis and a keratin and/or keratin polymer-containing medium. Molecular weights of ingredients in the macromolecular component are greater than or equal to 3 kDa and are 3-1000 kDa, and molecular weights of ingredients in the small molecular component are less than 3 kDa and are 0.01-2.99 kDa.Type: ApplicationFiled: October 28, 2021Publication date: February 9, 2023Applicant: Industrial Technology Research InstituteInventors: Yin-Lung HAN, Chieh-Lun CHENG, Kai-Chun FAN, Pei-Jyuan GAO, Bo-Han CHEN
-
Patent number: 11414658Abstract: A tracer particle is provided. The tracer particle includes: a core structure; a nucleic acid molecule immobilized on the core structure; and a shell layer covering the core structure and the nucleic acid molecule; wherein the core structure has a first porosity, the shell layer has a second porosity, and the first porosity is greater than the second porosity.Type: GrantFiled: December 11, 2019Date of Patent: August 16, 2022Assignee: Industrial Technology Research InstituteInventors: Kai-Chun Fan, Yin-Lung Han, Pei-Jyuan Gao, Yong-Yang Lin, Chieh-Lun Cheng, Chien-Chang Huang, Yung-Ho Chang, Chia-Long Lin, I-Son Ng, Bo-Han Chen
-
Publication number: 20210240907Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.Type: ApplicationFiled: April 21, 2021Publication date: August 5, 2021Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien-Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
-
Patent number: 10990744Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.Type: GrantFiled: January 11, 2018Date of Patent: April 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
-
Publication number: 20200199585Abstract: A tracer particle is provided. The tracer particle includes: a core structure; a nucleic acid molecule immobilized on the core structure; and a shell layer covering the core structure and the nucleic acid molecule; wherein the core structure has a first porosity, the shell layer has a second porosity, and the first porosity is greater than the second porosity.Type: ApplicationFiled: December 11, 2019Publication date: June 25, 2020Applicant: Industrial Technology Research InstituteInventors: Kai-Chun FAN, Yin-Lung HAN, Pei-Jyuan GAO, Yong-Yang LIN, Chieh-Lun CHENG, Chien-Chang HUANG, Yung-Ho CHANG, Chia-Long LIN, I-Son NG, Bo-Han CHEN
-
Publication number: 20180137233Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.Type: ApplicationFiled: January 11, 2018Publication date: May 17, 2018Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
-
Patent number: 9870443Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.Type: GrantFiled: November 23, 2015Date of Patent: January 16, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
-
Publication number: 20160085906Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.Type: ApplicationFiled: November 23, 2015Publication date: March 24, 2016Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
-
Patent number: 9195134Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.Type: GrantFiled: August 1, 2013Date of Patent: November 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Min Huang, Bo-Han Chen, Lun-Wen Yeh, Shun-Shing Yang, Chia-Cheng Chang, Chern-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin
-
Publication number: 20150040081Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.Type: ApplicationFiled: August 1, 2013Publication date: February 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Min Huang, Bo-Han Chen, Lun-Wen Yeh, Shun-Shing Yang, Chia-Cheng Chang, Chern-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin
-
Patent number: 8836165Abstract: Disclosed is a dual-source converter for a hybrid power supply. The converter includes a first power circuit, a second power circuit, an auxiliary circuit, an output circuit and a closed loop circuit. The first power circuit is electrically connected to the second power circuit in series for receiving two varied voltage sources. The auxiliary circuit is configured to achieve soft switching of all switches. The closed loop circuit is configured to control the duty cycles of the first power circuit, the second power circuit and the auxiliary circuit so as to improve the efficiency of the dual-source converter.Type: GrantFiled: December 14, 2010Date of Patent: September 16, 2014Assignee: Chung-Shan Institute of Science and Technology, Armaments, Bureau, Ministry of National DefenseInventors: Jung-Tzung Wei, Chung-You Lin, Bo-Han Chen, Kuo-Kuang Jen, Yu-Min Liao
-
Publication number: 20120007433Abstract: Disclosed is a dual-source converter for a hybrid power supply. The converter includes a first power circuit, a second power circuit, an auxiliary circuit, an output circuit and a closed loop circuit. The first power circuit is electrically connected to the second power circuit in series for receiving two varied voltage sources. The auxiliary circuit is configured to achieve soft switching of all switches. The closed loop circuit is configured to control the duty cycles of the first power circuit, the second power circuit and the auxiliary circuit so as to improve the efficiency of the dual-source converter.Type: ApplicationFiled: December 14, 2010Publication date: January 12, 2012Applicant: Chung-Shan Institute of Science and Technology Armaments, Bureau, Ministry of National DefenseInventors: Jung-Tzung Wei, Chung-You Lin, Bo-Han Chen, Kuo-Kuang Jen, Yu-Min Liao