Patents by Inventor Bo Hao

Bo Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250015054
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Application
    Filed: September 18, 2024
    Publication date: January 9, 2025
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching HO, Bo-Hao MA, Yu-Ting XUE, Ching-Hung TSENG, Guan-Hua LU, Hong-Da CHANG
  • Patent number: 12166533
    Abstract: Example test methods and apparatus are described. One example method includes receiving an uplink radio frequency signal by a test device from a terminal device, where the uplink radio frequency signal is generated by superimposing at least two test signals, and each of the at least two test signal corresponds to one communication protocol. The test device extracts the at least two test signals from the uplink radio frequency signal. The test device separately tests the at least two test signals, and obtains an uplink test result of the terminal device.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: December 10, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Bo Hao, Yecun Huang, Liang Hu, Jutian Guo, Wei Zhai, Chengwen Yan
  • Patent number: 12125828
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Grant
    Filed: September 11, 2023
    Date of Patent: October 22, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
  • Patent number: 12081206
    Abstract: A voltage-mode transmitter includes a serializer, a pre-driver circuit, a driver circuit, and a resistor calibration circuit. The serializer converts a data into a serial data. The pre-driver circuit drives the serial data. The driver circuit includes a slice, a replica slice, a reference voltage generation circuit, a first operational amplifier, and a second operational amplifier. The reference voltage generation circuit is coupled between a first system voltage and a second system voltage and includes a resistor. The resistor calibration circuit is configured to use a first current source and a reference resistor to generate a reference voltage, the first current source being a current source having been calibrated by a bandgap reference (BGR) circuit; to generate a target voltage by causing a current of a second current source to flow through the resistor; and to adjust the resistor according to the reference voltage and the target voltage.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: September 3, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Bo-Hao Hsu
  • Publication number: 20240244463
    Abstract: This application provides a radio resource measurement method and apparatus. The method includes: determining frequency domain resources of a narrowband on which an RSS pilot is located, where the RSS pilot occupies a part of the frequency domain resources of the narrowband; and determining, based on the frequency domain resource of the narrowband, a first radio resource measurement result corresponding to the RSS pilot. According to the method, UE can determine, based on the frequency domain resource of the narrowband occupied by the RSS pilot, the first radio resource measurement result corresponding to the RSS pilot.
    Type: Application
    Filed: March 28, 2024
    Publication date: July 18, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Weidong HE, Bo HAO, Li ZHANG, Yubo YANG, Pan LIU
  • Publication number: 20240120161
    Abstract: A keyboard device includes plural keycaps, a base plate, plural connecting elements and a circuit board. The plural connecting elements are connected with the respective keycaps and the base plate. The circuit board is located over the base plate. The circuit board includes plural membrane switches and plural first capacitance sensing units. When one of the first capacitance sensing units detects an approaching conductor or detects a motion of the conductor, a driving signal is generated or a control signal is outputted.
    Type: Application
    Filed: October 25, 2022
    Publication date: April 11, 2024
    Inventors: Chin-Sung Pan, Bo-Hao Su, Chen-Hsuan Hsu
  • Patent number: 11923337
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 5, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
  • Publication number: 20230420420
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching HO, Bo-Hao MA, Yu-Ting XUE, Ching-Hung TSENG, Guan-Hua LU, Hong-Da CHANG
  • Publication number: 20230282626
    Abstract: A high-bandwidth package-on-package (HBPoP) structure includes a first package structure and a second package structure disposed over the first package structure. The first package structure includes a first package substrate, a semiconductor die, an interposer, and a molding material. The first package substrate is formed of a silicon and/or ceramic material. The semiconductor die is disposed over the first package substrate. The interposer is disposed over the semiconductor die and is formed of a silicon and/or ceramic material. The molding material is disposed between the first package substrate and the interposer and surrounds the semiconductor die.
    Type: Application
    Filed: February 2, 2023
    Publication date: September 7, 2023
    Inventors: Tai-Yu CHEN, Bo-Jiun YANG, Tsung-Yu PAN, Yin-Fa CHEN, Ta-Jen YU, Bo-Hao MA, Wen-Sung HSU, Yao-Pang HSU
  • Publication number: 20230282625
    Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate. The logic die has a thickness of 125-350 micrometers. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills into the gap between the bottom substrate and the top substrate and sealing the logic die and the plurality of copper cored solder balls in the gap.
    Type: Application
    Filed: February 9, 2023
    Publication date: September 7, 2023
    Applicant: MEDIATEK INC.
    Inventors: Ta-Jen Yu, Shih-Chin Lin, Tai-Yu Chen, Bo-Jiun Yang, Bing-Yeh Lin, Yung-Cheng Huang, Wen-Sung Hsu, Bo-Hao Ma, Isabella Song
  • Publication number: 20230260866
    Abstract: A semiconductor package structure includes a package substrate, a semiconductor die, an interposer, an adhesive layer, and a molding material. The semiconductor die is disposed over the package substrate. The interposer is disposed over the semiconductor die. The adhesive layer connects the semiconductor die and the interposer. The molding material surrounds the semiconductor die and the adhesive layer.
    Type: Application
    Filed: January 20, 2023
    Publication date: August 17, 2023
    Inventors: Yin-Fa CHEN, Bo-Jiun YANG, Ta-Jen YU, Bo-Hao MA, Chih-Wei CHANG, Tsung-Yu PAN, Tai-Yu CHEN, Shih-Chin LIN, Wen-Sung HSU
  • Publication number: 20230179200
    Abstract: A voltage-mode transmitter includes a serializer, a pre-driver circuit, a driver circuit, and a resistor calibration circuit. The serializer converts a data into a serial data. The pre-driver circuit drives the serial data. The driver circuit includes a slice, a replica slice, a reference voltage generation circuit, a first operational amplifier, and a second operational amplifier. The reference voltage generation circuit is coupled between a first system voltage and a second system voltage and includes a resistor. The resistor calibration circuit is configured to use a first current source and a reference resistor to generate a reference voltage, the first current source being a current source having been calibrated by a bandgap reference (BGR) circuit; to generate a target voltage by causing a current of a second current source to flow through the resistor; and to adjust the resistor according to the reference voltage and the target voltage.
    Type: Application
    Filed: September 23, 2022
    Publication date: June 8, 2023
    Inventor: BO-HAO HSU
  • Publication number: 20230046413
    Abstract: A semiconductor assembly package is provided. The semiconductor package assembly includes a system-on-chip (SOC) package, a memory package and a heat spreader. The SOC package includes a logic die and a first substrate. The logic die has pads on it. The first substrate is electrically connected to the logic die by the pads. The memory package includes a second substrate and a memory die. The second substrate has a top surface and a bottom surface. The memory die is mounted on the top surface of the second substrate and is electrically connected to the second substrate using bonding wires. The heat spreader is disposed between the SOC package and the memory package, wherein the heat spreader is in contact with a back surface of the logic die away from the pads.
    Type: Application
    Filed: July 15, 2022
    Publication date: February 16, 2023
    Inventors: Tai-Yu CHEN, Chin-Lai CHEN, Hsiao-Yun CHEN, Wen-Sung HSU, Haw-Kuen SU, Duen-Yi HO, Bo-Jiun YANG, Ta-Jen YU, Bo-Hao MA
  • Publication number: 20220216926
    Abstract: Example test methods and apparatus are described. One example method includes receiving an uplink radio frequency signal by a test device from a terminal device, where the uplink radio frequency signal is generated by superimposing at least two test signals, and each of the at least two test signal corresponds to one communication protocol. The test device extracts the at least two test signals from the uplink radio frequency signal. The test device separately tests the at least two test signals, and obtains an uplink test result of the terminal device.
    Type: Application
    Filed: March 23, 2022
    Publication date: July 7, 2022
    Inventors: Bo HAO, Yecun HUANG, Liang HU, Jutian GUO, Wei ZHAI, Chengwen YAN
  • Publication number: 20220130769
    Abstract: An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 28, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching HO, Bo-Hao MA, Chee-Key CHUNG
  • Patent number: 11315881
    Abstract: An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: April 26, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Chee-Key Chung
  • Patent number: 11289346
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: March 29, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
  • Patent number: 11238961
    Abstract: A method, device, and computer program storage product for generating a query to extract clinical features into a set of electronic medical record (EMR) tables based on clinical knowledge. A knowledge tree is constructed according to a set of clinical knowledge data. An EMR graph corresponding to a set of EMR tables is obtained. The EMR graph comprises at set of table nodes and a set of attribute nodes. The set of table nodes and the set of attribute nodes represent a structure of each EMR table in the set of EMR tables and a reference relationship among attributes of set of EMR tables. A plurality of sub-queries is generated based on the knowledge tree and the EMR graph. At least one query is generated by combining the plurality of sub-queries according to the knowledge tree.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Bi Bo Hao, Gang Hu, Jing Li, Wen Sun, Guo Tong Xie, Yi Qin Yu
  • Patent number: 11227842
    Abstract: Provided is a substrate structure, including a substrate having at least one chamfer formed on a surface thereof, and a plurality of conductive bodies formed to the substrate. Therefore, a stress generated during the packaging process is alleviated through the chamfer, and the substrate structure is prevented from being cracked. An electronic package employing the substrate structure is also provided.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 18, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Hao Wang, Chang-Fu Lin, Chun-Tang Lin, Bo-Hao Chang
  • Patent number: D1070647
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: April 15, 2025
    Assignee: Douyin Vision (Beijing) Co., Ltd.
    Inventors: Bo Hao, Qing Yang, Jingyi Zhao, Binfeng Xiong