Patents by Inventor Bo-Hao Ma
Bo-Hao Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250015054Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.Type: ApplicationFiled: September 18, 2024Publication date: January 9, 2025Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chi-Ching HO, Bo-Hao MA, Yu-Ting XUE, Ching-Hung TSENG, Guan-Hua LU, Hong-Da CHANG
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Patent number: 12125828Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.Type: GrantFiled: September 11, 2023Date of Patent: October 22, 2024Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
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Patent number: 11923337Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.Type: GrantFiled: August 29, 2019Date of Patent: March 5, 2024Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
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Publication number: 20230420420Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chi-Ching HO, Bo-Hao MA, Yu-Ting XUE, Ching-Hung TSENG, Guan-Hua LU, Hong-Da CHANG
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Publication number: 20230282626Abstract: A high-bandwidth package-on-package (HBPoP) structure includes a first package structure and a second package structure disposed over the first package structure. The first package structure includes a first package substrate, a semiconductor die, an interposer, and a molding material. The first package substrate is formed of a silicon and/or ceramic material. The semiconductor die is disposed over the first package substrate. The interposer is disposed over the semiconductor die and is formed of a silicon and/or ceramic material. The molding material is disposed between the first package substrate and the interposer and surrounds the semiconductor die.Type: ApplicationFiled: February 2, 2023Publication date: September 7, 2023Inventors: Tai-Yu CHEN, Bo-Jiun YANG, Tsung-Yu PAN, Yin-Fa CHEN, Ta-Jen YU, Bo-Hao MA, Wen-Sung HSU, Yao-Pang HSU
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Publication number: 20230282625Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate. The logic die has a thickness of 125-350 micrometers. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills into the gap between the bottom substrate and the top substrate and sealing the logic die and the plurality of copper cored solder balls in the gap.Type: ApplicationFiled: February 9, 2023Publication date: September 7, 2023Applicant: MEDIATEK INC.Inventors: Ta-Jen Yu, Shih-Chin Lin, Tai-Yu Chen, Bo-Jiun Yang, Bing-Yeh Lin, Yung-Cheng Huang, Wen-Sung Hsu, Bo-Hao Ma, Isabella Song
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Publication number: 20230260866Abstract: A semiconductor package structure includes a package substrate, a semiconductor die, an interposer, an adhesive layer, and a molding material. The semiconductor die is disposed over the package substrate. The interposer is disposed over the semiconductor die. The adhesive layer connects the semiconductor die and the interposer. The molding material surrounds the semiconductor die and the adhesive layer.Type: ApplicationFiled: January 20, 2023Publication date: August 17, 2023Inventors: Yin-Fa CHEN, Bo-Jiun YANG, Ta-Jen YU, Bo-Hao MA, Chih-Wei CHANG, Tsung-Yu PAN, Tai-Yu CHEN, Shih-Chin LIN, Wen-Sung HSU
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Publication number: 20230046413Abstract: A semiconductor assembly package is provided. The semiconductor package assembly includes a system-on-chip (SOC) package, a memory package and a heat spreader. The SOC package includes a logic die and a first substrate. The logic die has pads on it. The first substrate is electrically connected to the logic die by the pads. The memory package includes a second substrate and a memory die. The second substrate has a top surface and a bottom surface. The memory die is mounted on the top surface of the second substrate and is electrically connected to the second substrate using bonding wires. The heat spreader is disposed between the SOC package and the memory package, wherein the heat spreader is in contact with a back surface of the logic die away from the pads.Type: ApplicationFiled: July 15, 2022Publication date: February 16, 2023Inventors: Tai-Yu CHEN, Chin-Lai CHEN, Hsiao-Yun CHEN, Wen-Sung HSU, Haw-Kuen SU, Duen-Yi HO, Bo-Jiun YANG, Ta-Jen YU, Bo-Hao MA
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Publication number: 20220130769Abstract: An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield.Type: ApplicationFiled: December 15, 2020Publication date: April 28, 2022Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chi-Ching HO, Bo-Hao MA, Chee-Key CHUNG
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Patent number: 11315881Abstract: An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield.Type: GrantFiled: December 15, 2020Date of Patent: April 26, 2022Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chi-Ching Ho, Bo-Hao Ma, Chee-Key Chung
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Patent number: 11289346Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.Type: GrantFiled: July 2, 2020Date of Patent: March 29, 2022Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
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Patent number: 11195812Abstract: A method for fabricating an electronic package is provided. A plurality of packaging structures are provided, each of which having a carrier and at least one electronic component disposed on the carrier. The plurality of packaging structures are disposed on a supporting plate. An encapsulation layer is formed on the supporting plate and encapsulates the plurality of packaging structures. Even if there are various types of electronic packages of different specifications in the market, the molds that the encapsulation layer uses can still be developed for a supporting plate of a certain specification. Therefore, the fabrication cost of the electronic package is reduced.Type: GrantFiled: March 17, 2020Date of Patent: December 7, 2021Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Hsin-Yi Liao, Cheng-Kai Chang, Bo-Hao Ma, Chun-Chi Ke
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Publication number: 20210175196Abstract: A method for fabricating an electronic package is provided. A plurality of packaging structures are provided, each of which having a carrier and at least one electronic component disposed on the carrier. The plurality of packaging structures are disposed on a supporting plate. An encapsulation layer is formed on the supporting plate and encapsulates the plurality of packaging structures. Even if there are various types of electronic packages of different specifications in the market, the molds that the encapsulation layer uses can still be developed for a supporting plate of a certain specification. Therefore, the fabrication cost of the electronic package is reduced.Type: ApplicationFiled: March 17, 2020Publication date: June 10, 2021Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Hsin-Yi Liao, Cheng-Kai Chang, Bo-Hao Ma, Chun-Chi Ke
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Publication number: 20200350285Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.Type: ApplicationFiled: August 29, 2019Publication date: November 5, 2020Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
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Publication number: 20200335447Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.Type: ApplicationFiled: July 2, 2020Publication date: October 22, 2020Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
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Patent number: 10741500Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.Type: GrantFiled: May 4, 2018Date of Patent: August 11, 2020Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
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Publication number: 20190237374Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.Type: ApplicationFiled: May 4, 2018Publication date: August 1, 2019Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma