Abstract: Disclosed herein is a mobile communication terminal equipped with a camera having an image distortion compensation function which compensates image distortion created by a luminance difference between pixels in the vicinity of a central portion of a pixel array of an image sensor and pixels in the vicinity of an outer portion of a pixel array of the image sensor by detecting a Y-component value of the central pixel of the pixel array of the image sensor and Y-component values of the pixels located diagonally to the central pixel, comparing the Y-component value of the central pixel with the Y-component values of the pixels located diagonally to the central pixel, generating compensation values for compensating signal distortion in each of the pixels located diagonally to the central pixel according to the comparison result, and outputting a distortion compensation command, together with the compensation values, to the ISP (image signal processor).

Abstract: A hardware scheduler for a grooming switch with at least three switching stages accumulates a list of connection requests that cannot be granted given currently granted connection assignments. At a designated time, two data structures are dynamically built: an xRAM which records, for each output of a switch slice, which input is currently assigned to that output; and a yRAM which records, for each of the same outputs, the output of a second switch slice that is connected to a corresponding input of the second switch slice. Connections are assigned to satisfy the stored unassigned requests, by reassigning existing connection assignments using the xRAM and yRAM data structures.

Abstract: A dual-interface computer interface card includes a circuit board. The circuit board includes an ExpressCard connector, a USB connector, a control circuit, a converter, two USB signal traces, two DC traces. The two USB traces are electrically connected with the ExpressCard connector and the USB connector respectively. The two DC traces are electrically connected with the converter and respectively with the ExpressCard and USB connectors. The control circuit, subject to the required DC operation voltage, is optionally connected with one of the two DC traces, while another DC trace is connected with the converter to convert its DC voltage level into the DC voltage level required by the control circuit. Accordingly, the computer interface card can be connected with the computer system optionally by one of the connectors thereof for transmission of USB signals therebetween.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.

Abstract: An apparatus and method for processing data using the complex quadrature phase shift keying (CQPSK) is disclosed. The present invention includes plurality of multiplying units for multiplying a long pseudo noise (PN) code with an in-phase pseudo noise and quadrature pseudo noise, and a results of multiplying with a pilot channel, a dedicated control channel, a voice channel, a high-speed data transmission channel, a result multiplied with channels with gain, filtering units for eliminating noise, subtracting and adding units for calculating final result, and in-phase/quadrature channel outputting unit for outputting I-channel/Q-channel. The present invention can improve data processing speed of a radio channel, increase capacity of data processing in radio communication and also can be applicable to various kinds of radio communication devices transceiving voice, media contents and high-speed data at a same time.

Abstract: Disclosed herein is a mobile communication terminal equipped with a camera having an image distortion compensation function which compensates image distortion created by a luminance difference between pixels in the vicinity of a central portion of a pixel array of an image sensor and pixels in the vicinity of an outer portion of a pixel array of the image sensor by detecting a Y-component value of the central pixel of the pixel array of the image sensor and Y-component values of the pixels located diagonally to the central pixel, comparing the Y-component value of the central pixel with the Y-component values of the pixels located diagonally to the central pixel, generating compensation values for compensating signal distortion in each of the pixels located diagonally to the central pixel according to the comparison result, and outputting a distortion compensation command, together with the compensation values, to the ISP (image signal processor).

Abstract: Disclosed is a technique for processing pixel array data of a mobile terminal with a digital camera function. A device for processing pixel array data includes: an image sensor having (x×y)-sized pixel capacity, converting an optical signal received via a lens into an electric signal, and generating (x×y)-sized pixel array data; and an image signal processor for generating an (X×Y)-sized extended pixel array data area, receiving pixel values of the (x×y)-sized pixel array data from the image sensor, arranging the pixel values of the (x×y)-sized pixel array data in the (X×Y)-sized extended pixel array data area, arranging pixel values obtained by performing an arithmetical operation on pixel values of (x×y)-sized pixel array data, adjacent to remaining pixel areas of the (X×Y)-sized extended pixel array data other than the pixel areas having the pixel values of the (x×y)-sized pixel array data, in the remaining pixel areas, and outputting the (X×Y)-sized extended pixel array data.

Abstract: Disclosed is a mobile communication terminal capable of taking a picture and allowing a user to view TV. The mobile communication terminal includes: a display unit; a camera unit for converting an optical signal inputted through a lens system into an electrical signal and outputting the electrical signal; a TV reception unit for extracting an image signal from a TV signal received over the air; and a signal processing unit for alternatively processing a first image signal outputted from the camera unit or a second image signal outputted from the TV reception unit, and outputting the processed image signal to the display unit.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: A hardware scheduler for a grooming switch with at least three switching stages accumulates a list of connection requests that cannot be granted given currently granted connection assignments. At a designated time, two data structures are dynamically built: an xRAM which records, for each output of a switch slice, which input is currently assigned to that output; and a yRAM which records, for each of the same outputs, the output of a second switch slice that is connected to a corresponding input of the second switch slice. Connections are assigned to satisfy the stored unassigned requests, by reassigning existing connection assignments using the xRAM and yRAM data structures.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: An apparatus and method for processing data using the complex quadrature phase shift keying (CQPSK) is disclosed. The present invention includes plurality of multiplying units for multiplying a long pseudo noise (PN) code with an in-phase pseudo noise and quadrature pseudo noise, and a results of multiplying with a pilot channel, a dedicated control channel, a voice channel, a high-speed data transmission channel, a result multiplied with channels with gain, filtering units for eliminating noise, subtracting and adding units for calculating final result, and in-phase/quadrature channel outputting unit for outputting I-channel/Q-channel. The present invention can improve data processing speed of a radio channel, increase capacity of data processing in radio communication and also can be applicable to various kinds of radio communication devices transceiving voice, media contents and high-speed data at a same time.

Abstract: A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.