Abstract: Disclosed are an apparatus for diagnosing a state of a battery and a method thereof. The apparatus diagnoses the state of the battery with high accuracy in a short time period by obtaining first state information of the battery from a battery management system (BMS), obtaining second state information of the battery from electrochemical impedance spectroscopy (EIS) equipment, obtaining third state information of the battery from a history management server, and diagnosing the state of the battery based on the first state information, the second state information and the third state information.

Abstract: In an apparatus for correcting a voltage of a battery cell and a method thereof. The apparatus includes a voltage sensor configured for measuring voltages of a plurality of battery cells, and a controller which is configured for determining an amount of voltage change of each battery cell corresponding to a preset discharge current, detects target battery cells whose identification numbers have preset intervals while the amount of voltage change does not exceed a threshold value, and corrects the amount of voltage change of each target battery cell.

Abstract: Provided is a superwide pouch type secondary battery comprising an electrode assembly including a cathode plate, an anode plate, and a separator; a pouch surrounding the electrode assembly; and electrode tabs connected to both ends of the electrode assembly and protruding outward of the pouch, wherein the electrode tabs connected to the both ends of the electrode assembly include one or more cathode tabs and anode tabs, respectively, and width of battery cell is more than 4 times longer than height of battery cell such that loading efficiency of the pouch type secondary battery into a vehicle and an energy density may be improved without increasing an internal electrode.

Abstract: A battery module includes a module case, a battery cell assembly that is received in the module case, a heat sink mounted below the module case, and a heat pipe member mounted inside an upper side of the module case. The battery cell assembly includes battery cells, each of which has an electrode lead drawn to one or two sides thereof. The battery cells are stacked along a horizontal direction of the module case such that an edge of each of the battery cells not having an electrode lead is oriented downwardly facing the heat sink. The heat pipe member includes an evaporator and a condenser, the evaporator being formed on a side of the electrode leads of the battery cells, and the condenser being in contact with an inner surface of the module case.

Abstract: Provided is a superwide pouch type secondary battery comprising an electrode assembly including a cathode plate, an anode plate, and a separator; a pouch surrounding the electrode assembly; and electrode tabs connected to both ends of the electrode assembly and protruding outward of the pouch, wherein the electrode tabs connected to the both ends of the electrode assembly include one or more cathode tabs and anode tabs, respectively, and width of battery cell is more than 4 times longer than height of battery cell such that loading efficiency of the pouch type secondary battery into a vehicle and an energy density may be improved without increasing an internal electrode.

Abstract: Provided is a superwide pouch type secondary battery comprising an electrode assembly including a cathode plate, an anode plate, and a separator; a pouch surrounding the electrode assembly; and electrode tabs connected to both ends of the electrode assembly and protruding outward of the pouch, wherein the electrode tabs connected to the both ends of the electrode assembly include one or more cathode tabs and anode tabs, respectively, and width of battery cell is more than 4 times longer than height of battery cell such that loading efficiency of the pouch type secondary battery into a vehicle and an energy density may be improved without increasing an internal electrode.

Abstract: A battery module includes a module case, a battery cell assembly that is received in the module case, a heat sink mounted below the module case, and a heat pipe member mounted inside an upper side of the module case. The battery cell assembly includes battery cells, each of which has an electrode lead drawn to one or two sides thereof. The battery cells are stacked along a horizontal direction of the module case such that an edge of each of the battery cells not having an electrode lead is oriented downwardly facing the heat sink. The heat pipe member includes an evaporator and a condenser, the evaporator being formed on a side of the electrode leads of the battery cells, and the condenser being in contact with an inner surface of the module case.

Abstract: Provided is a superwide pouch type secondary battery comprising an electrode assembly including a cathode plate, an anode plate, and a separator; a pouch surrounding the electrode assembly; and electrode tabs connected to both ends of the electrode assembly and protruding outward of the pouch, wherein the electrode tabs connected to the both ends of the electrode assembly include one or more cathode tabs and anode tabs, respectively, and width of battery cell is more than 4 times longer than height of battery cell such that loading efficiency of the pouch type secondary battery into a vehicle and an energy density may be improved without increasing an internal electrode.

Abstract: Disclosed are layers and patterns of nanowire or nanotube using a chemical self assembly for forming a semiconductor layer and a conductive layer of a thin film transistor by using a nanowire and/or nanotube solution and an diamine-based self-assembled monolayer (SAM) material. The Layers and patterns including layers and patterns of nanowire or nanotube using a chemical self assembly include: a substrate having a surface terminated with amine group (—NH2) by using a chemical self-assembled monolayer (SAM) material having at least one end terminated with amine group(—NH2); and a first nanowire or nanotube layer ionically coupled to the amine group (—NH2) of the surface of the substrate.

Abstract: A thin film transistor (TFT) array substrate and a method for fabricating the thin film transistor (TFT) array substrate is disclosed, wherein a passivation layer is directly subjected to exposing and patterning processes without using any photoresist, thereby simplifying the fabrication process and ensuring reduced preparation costs.

Abstract: A gallium nitride (GaN) bonded substrate and a method of manufacturing a GaN bonded substrate in which a polycrystalline nitride-based substrate is used. The method includes loading a single crystalline GaN substrate and a polycrystalline nitride substrate into a bonder; raising the temperature in the bonder; bonding the single crystalline GaN substrate and the polycrystalline nitride substrate together by pressing the single crystalline GaN substrate and the polycrystalline nitride substrate against each other after the step of raising the temperature; and cooling the resultant bonded substrate.

Abstract: Provided are a method of fabricating a stamp, a thin film transistor and a liquid crystal display device using the same. The stamp has an improved contact property with respect to a substrate. A charged zone is formed on the substrate using the stamp, and nano material charged with opposite charges to those of the charged zone is coated or plated to form a self-assembled monolayer (SAM). Therefore, the thin film transistor and the liquid crystal display device can have precise nano patterns, thereby improving the performance of the device.

Abstract: A thin film transistor (TFT) including a nanowire semiconductor layer having nanowires aligned in one direction in a channel region is disclosed. The nanowire semiconductor layer is selectively formed in the channel region. A method for fabricating the TFT, a liquid crystal display (LCD) device using the TFT, and a method for manufacturing the LCD device are also disclosed. The TFT fabricating method includes forming alignment electrodes on the insulating film such that the alignment electrodes face each other, to define a channel region, forming an organic film, to expose the channel region, coating a nanowire-dispersed solution on an entire surface of a substrate including the organic film, forming a nanowire semiconductor layer in the channel region by generating an electric field between the alignment electrodes such that nanowires of the nanowire semiconductor layer are aligned in a direction, and removing the organic film.

Abstract: A thin film transistor (TFT) array substrate and a method for fabricating the thin film transistor (TFT) array substrate is disclosed, wherein a passivation layer is directly subjected to exposing and patterning processes without using any photoresist, thereby simplifying the fabrication process and ensuring reduced preparation costs.

Abstract: Disclosed are layers and patterns of nanowire or nanotube using a chemical self assembly for forming a semiconductor layer and a conductive layer of a thin film transistor by using a nanowire and/or nanotube solution and an diamine-based self-assembled monolayer (SAM) material. The Layers and patterns including layers and patterns of nanowire or nanotube using a chemical self assembly include: a substrate having a surface terminated with amine group (—NH2) by using a chemical self-assembled monolayer (SAM) material having at least one end terminated with amine group(—NH2); and a first nanowire or nanotube layer ionically coupled to the amine group (—NH2) of the surface of the substrate.

Abstract: A thin film transistor (TFT) array substrate and a method for fabricating the thin film transistor (TFT) array substrate is disclosed, wherein a passivation layer is directly subjected to exposing and patterning processes without using any photoresist, thereby simplifying the fabrication process and ensuring reduced preparation costs.

Abstract: Disclosed are layers and patterns of nanowire or nanotube using a chemical self assembly for forming a semiconductor layer and a conductive layer of a thin film transistor by using a nanowire and/or nanotube solution and an diamine-based self-assembled monolayer (SAM) material. The Layers and patterns including layers and patterns of nanowire or nanotube using a chemical self assembly include: a substrate having a surface terminated with amine group (—NH2) by using a chemical self-assembled monolayer (SAM) material having at least one end terminated with amine group (—NH2); and a first nanowire or nanotube layer ionically coupled to the amine group (—NH2) of the surface of the substrate.

Abstract: A thin film transistor (TFT) including a nanowire semiconductor layer having nanowires aligned in one direction in a channel region is disclosed. The nanowire semiconductor layer is selectively formed in the channel region. A method for fabricating the TFT, a liquid crystal display (LCD) device using the TFT, and a method for manufacturing the LCD device are also disclosed. The TFT fabricating method includes forming alignment electrodes on the insulating film such that the alignment electrodes face each other, to define a channel region, forming an organic film, to expose the channel region, coating a nanowire-dispersed solution on an entire surface of a substrate including the organic film, forming a nanowire semiconductor layer in the channel region by generating an electric field between the alignment electrodes such that nanowires of the nanowire semiconductor layer are aligned in a direction, and removing the organic film.

Abstract: A method of manufacturing a thin film transistor includes: forming a gate insulating layer on a substrate having a gate electrode; forming a semiconductor layer of nanomaterial on the gate insulating layer; forming a source electrode and a drain electrode on the gate insulating layer; and applying a voltage to the source electrode and the drain electrode to arrange a direction of the nanomaterial.

Abstract: An apparatus for fabricating a flat panel display device including a preparation unit to form a thin film layer and a etch-resist on a substrate and a hard mold to mold the etch-resist, the hard mold including a back plate and a molding pattern.