Abstract: A bus configuration system includes a plurality of driver integrated circuits (ICs) coupled sequentially on a daisy chain, and a bus controller coupled to the plurality of driver ICs. Each driver IC includes a plurality of ports. The bus controller is used to generate a port definition code for configuring each port of the each driver IC. The bus controller includes a clock output port used to output a clock signal and a data output port used to output a data signal. When a port of the plurality of ports detects the clock signal, the port is configured as a clock input port.

Abstract: A memory device includes a semiconductor substrate and a memory cell at a memory region of the semiconductor substrate. A memory cell includes a memory portion of the semiconductor substrate, a tunneling layer, a storage layer, a first electrode, and a second electrode. The tunneling layer is over the memory portion of the semiconductor substrate. The storage layer is over and in contact with the tunneling layer. The first electrode is over the storage layer. The second electrode is over and in contact with the tunneling layer but is spaced apart from the storage layer.

Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.

Abstract: A multi-window switching method and a switching system are provided. The multi-window switching method includes following steps: displaying a first window screen provided via a first computer device and a second window screen provided via a second computer device, wherein a first screen boundary of the first window screen is adjacent to a second screen boundary of the second window screen; receiving a control signal provided by an input device to control a position of a cursor on the first window screen or the second window screen; calculating a first moving speed of the input device when the cursor touches the first screen boundary in the first window screen; and determining whether the first moving speed is greater than or equal to a preset speed threshold to decide whether the cursor is displayed in the second window screen.

Abstract: A data transmission method, applied to a data transmission device connected to a first host and a second host, comprising: (a) activating a console of the first host via a trigger operation and acquiring a source path of target data in the first host; (b) acquiring the target data from the source path and copying the target data to a storage circuit inside or outside the data transmission device; and (c) copying the target data from the storage circuit to the second host.

Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.

Abstract: A multi-window switching method and a switching system are provided. The multi-window switching method includes following steps: displaying a first window screen provided via a first computer device and a second window screen provided via a second computer device, wherein a first screen boundary of the first window screen is adjacent to a second screen boundary of the second window screen; receiving a control signal provided by an input device to control a position of a cursor on the first window screen or the second window screen; calculating a first moving speed of the input device when the cursor touches the first screen boundary in the first window screen; and determining whether the first moving speed is greater than or equal to a preset speed threshold to decide whether the cursor is displayed in the second window screen.

Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.

Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.