Abstract: An input buffer circuit comprising: a first current source; a first differential control circuit, configured to generate a first bias voltage at the first couple terminal according to the input signals, and configured to generate first control signals according to the input signals; a second current source; a second differential control circuit, configured to generate a second bias voltage at the second couple terminal according to the input signals, and configured to generate second control signals according to the input signals; a third current source, configured to provide a first current according to the second bias voltage; a first differential output circuit, configured to receive the first control signals to generate output signals; a fourth current source, configured to drain a second current according to the first bias voltage; and a second differential output circuit, configured to receive the second control signals to generate the output signal.

Abstract: An input buffer circuit comprising: a first current source; a first differential control circuit, configured to generate a first bias voltage at the first couple terminal according to the input signals, and configured to generate first control signals according to the input signals; a second current source; a second differential control circuit, configured to generate a second bias voltage at the second couple terminal according to the input signals, and configured to generate second control signals according to the input signals; a third current source, configured to provide a first current according to the second bias voltage; a first differential output circuit, configured to receive the first control signals to generate output signals; a fourth current source, configured to drain a second current according to the first bias voltage; and a second differential output circuit, configured to receive the second control signals to generate the output signal.

Abstract: A latch apparatus and applications thereof are provided. The latch apparatus consists of a latch circuit and a switchable DC block unit. The switchable DC block unit is coupled to the latch circuit, and configured to: isolate a cross-coupling path in the latch circuit and store a voltage difference before the latch apparatus performs the latching operation; and when the latch apparatus performs the latching operation, provide the stored voltage varying with time to increase the overdrive voltage of at least one transistor in the latch circuit (increase the transistor transconductance), so that the latch apparatus maintains high speed operation at low supply voltage.

Abstract: A latch, an operation method of the latch, and a comparator using the latch are disclosed. The latch includes first and second cross-coupled pairs and first and second transistor pairs. First terminals of the first and second current paths of the first cross-coupled pair are respectively coupled to first terminals of the first and second transistors of the first transistor pair. First terminals of the third and fourth current paths of the second cross-coupled pair are respectively coupled to first terminals of the third and fourth transistors of the second transistor pair. Control terminals of the third and fourth transistors are respectively coupled to the first and second current paths. Control terminals of the first and second transistors are respectively coupled to the third and fourth current paths.

Abstract: A latch apparatus and applications thereof are provided. The latch apparatus consists of a latch circuit and a switchable DC block unit. The switchable DC block unit is coupled to the latch circuit, and configured to: isolate a cross-coupling path in the latch circuit and store a voltage difference before the latch apparatus performs the latching operation; and when the latch apparatus performs the latching operation, provide the stored voltage varying with time to increase the overdrive voltage of at least one transistor in the latch circuit (increase the transistor transconductance), so that the latch apparatus maintains high speed operation at low supply voltage.