Abstract: A device includes a substrate, a gate structure, a capping layer, a source/drain region, a source/drain contact, and an air spacer. The gate structure wraps around at least one vertical stack of nanostructure channels over the substrate. The capping layer is on the gate structure. The source/drain region abuts the gate structure. The source/drain contact is on the source/drain region. The air spacer is between the capping layer and the source/drain contact.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first stacked nanostructure, and forming a first via adjacent to the first stacked nanostructure. The method includes forming a dummy gate structure over the first stacked nanostructure and the first via, and removing a portion of the first stacked nanostructure to form a trench. The method includes forming a first S/D structure in the trench, and a top surface of the first S/D structure is higher than a top surface of the first via. The method includes replacing the dummy gate structure with a gate structure, and the gate structure includes a gate dielectric layer and a gate electrode layer over the gate dielectric layer, and the gate electrode layer includes at least one metal layer. The method includes forming a first contact structure over the first S/D structure.

Abstract: A semiconductor device is provided. The semiconductor device has a stack of parallel metal gates formed on a first side of a substrate, a first pair of insulation regions extending across the stack of parallel metal gates, a second pair of insulation regions replacing two of the parallel metal gates, a first isolated region enclosed by the first and second pairs of insulation layers, a first via formed within the isolated region, and an insulation layer replacing the metal gates located within the isolated region. Tree or more metal gates are located within the isolated region, and the first via extends through a portion of a center one of the three metal gates within the isolated region.

Abstract: A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.

Abstract: An electrolyte, a preparation method thereof and a lithium ion battery, where the electrolyte comprises a solvent, a lithium salt, and a first additive shown in Formula 1; in Formula 1, R1 and R3 are each independently selected from a substituted or unsubstituted C1-C20 alkyl group, (—C2H4—O—C2H4—)n or is a direct bond, and 1?n?5; R2 is selected from one of —NH—, —CH2—, —SiH2—, —BH— and —PH—. The electrolyte has simple composition, and can not only enable the lithium ion battery to maintain excellent cycle performance at high voltages, but also effectively inhibit the lithium ion battery from overproducing gas so as to optimize storage performance.

Abstract: A semiconductor device includes a fin, first source/drain regions, second source/drain regions, a first nanosheet, a second nanosheet and a metal gate structure. The fin extends in a first direction and protrudes above an insulator. The first source/drain regions are over the fin. The second source/drain regions are over the first source/drain regions. The first nanosheet extends in the first direction between the first source/drain regions. The second nanosheet extends in the first direction between the second source/drain regions. The metal gate structure is over the fin and between the first source/drain regions. The metal gate structure extends in a second direction different from the first direction from a first sidewall to a second sidewall. A first distance in the second direction between the first nanosheet and the first sidewall is smaller than a second distance in the second direction between the first nanosheet and the second sidewall.

Abstract: An electrolytic solution includes an organic solvent, an electrolyte, and an additive. The additive includes a first compound represented by Formula 1, where R1 is selected from one of a single bond, substituted or unsubstituted alkoxy, C1-C6 alkylene, and C2-C6 alkenyl; R2 and R3 each are independently selected from one of substituted or unsubstituted alkoxy, C1-C6 alkylene, and C2-C6 alkenyl; and R4 is B or P. Since the first compound includes an N-containing group that may be combined with a protonic acid in the electrolytic solution, the electrolytic solution have good stability; moreover, the cycle performance of a lithium secondary battery is improved.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and the fin structure includes a plurality of nanostructures stacked in a vertical direction. The semiconductor device structure includes a gate structure formed over the fin structure, and an S/D structure formed adjacent to the gate structure. The semiconductor device structure includes a first via formed adjacent to the S/D structure, and a first contact structure formed over the S/D structure. The semiconductor device structure includes a second contact structure formed below the S/D structure, and the first via is in direct contact with the first contact structure and the second contact structure.

Abstract: A high-temperature and high-salt resistant hyperbranched lubricant for a water-based drilling fluid, and preparation and application thereof are provided, belonging to the technical field of oilfield chemistry. The preparation method includes the steps of: mixing tetraethyl orthosilicate (TEOS), diethanolamine (DEA), and triethanolamine (TEA) for a transesterification and polycondensation reaction to obtain highly reactive hyperbranched polysiloxane; adding an acrylamide (AM) monomer, an anionic monomer, and a polar ester monomer into deionized water to obtain a monomer solution; adjusting the pH of the monomer solution to 5-9, and then adding highly reactive hyperbranched polysiloxane; introducing nitrogen to remove oxygen, adding an initiator, and thermally initiating a polymerization reaction; and after the reaction is completed, vacuum-drying and crushing an obtained product to obtain the high-temperature and high-salt resistant hyperbranched lubricant for a water-based drilling fluid.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

Abstract: A semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. The first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. The first source/drain portion has a conductivity type different from that of the second source/drain portion. The first and second metal contacts are respectively formed on the first and second source/drain portions. The first conductive carbon layer is formed between the first source/drain portion and the first metal contact.

Abstract: A semiconductor structure includes a substrate, a first device unit and a second device unit. The substrate includes a first region and a second region. The first device unit is disposed on the first region, and includes a plurality of first channel portions and two first source/drain portions. The second device unit is disposed on the second region, and includes a lower device and an upper device. The lower device is disposed on the second region, and includes at least one lower channel portion and two lower source/drain portions. The upper device is disposed above and spaced apart from the lower device, and includes at least one upper channel portion and two upper source/drain portions. A number of the first channel portions is greater than a number of the at least one lower channel portion and greater than a number of the at least one upper channel portion.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes channel layers, a mask structure, a gate structure and a source/drain pattern. The channel layers are stacked vertically apart along a first direction over a substrate. The mask structure is disposed over and apart from the channel layers along the first direction. The gate structure laterally extends along a second direction perpendicular to the first direction disposed, wherein the gate structure wraps around the channel layers and laterally surround the mask structure. The source/drain pattern is in contact with the channel layers.

Abstract: Embodiments of the present disclosure provide semiconductor devices having a front side to backside conductive path through a source/drain feature. In some embodiments, the front side to backside conductive path may be formed through a source/drain feature in a standard cell. The other embodiments, the front side to backside conductive path is formed through a source/drain feature in a filler cell. The front side to backside conductive path enables flexible routing for local connections, backside signal connections, and/or backside power rail connection.

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

Abstract: A semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. The first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. The first source/drain portion has a conductivity type different from that of the second source/drain portion. The first and second metal contacts are respectively formed on the first and second source/drain portions. The first conductive carbon layer is formed between the first source/drain portion and the first metal contact.