Abstract: A resistive random access memory (RRAM) is provided. The RRAM includes a lower electrode, an upper electrode, a first variable resistance layer and a second variable resistance layer. The lower electrode is disposed on a substrate, and is a single electrode or a pair of electrodes electrically connected to each other. The upper electrode is disposed on the lower electrode, and overlaps the lower electrode. The first variable resistance layer and the second variable resistance layer are disposed on the substrate. At least a portion of the first variable resistance layer is disposed between the lower electrode and the upper electrode, and at least a portion of the second variable resistance layer is disposed between the lower electrode and the upper electrode and connected to the first variable resistance layer.

Abstract: A resistive random access memory (RRAM) and its manufacturing method are provided. The RRAM includes a substrate having an array region and a peripheral region. A plurality of memory cells and a gap-filling dielectric layer overlying the memory cells are located on the substrate and in the array region. A buffer layer only in the array region covers the gap-filling dielectric layer, and its material layer is different from that of the gap-filling dielectric layer. A first low-k dielectric layer is only located in the peripheral region, and its material is different from that of the buffer layer. A dielectric constant of the first low-k dielectric layer is less than 3. A top surface of the first low-k dielectric layer is coplanar with that of the buffer layer. A first conductive plug passes through the buffer layer and the gap-filling dielectric layer and contacts one of the memory cells.

Abstract: A resistive random access memory (RRAM) is provided. The RRAM includes a lower electrode, an upper electrode, a first variable resistance layer and a second variable resistance layer. The lower electrode is disposed on a substrate, and is a single electrode or a pair of electrodes electrically connected to each other. The upper electrode is disposed on the lower electrode, and overlaps the lower electrode. The first variable resistance layer and the second variable resistance layer are disposed on the substrate. At least a portion of the first variable resistance layer is disposed between the lower electrode and the upper electrode, and at least a portion of the second variable resistance layer is disposed between the lower electrode and the upper electrode and connected to the first variable resistance layer.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.

Abstract: A memory storage apparatus including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of memory cells. The memory cell array is configured to store data. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to apply one of a set signal and a reset signal to a target memory cell among the memory cells to generate a read current. The memory control circuit receives a read current of the target memory cell. The memory control circuit compares the read current with a reference current. The memory control circuit determines whether the target memory cell is failed according to a comparison result. In addition, a method for testing a memory storage apparatus is also provided.

Abstract: A key generator including a first access circuit, a first calculating circuit and a first certification circuit is provided. The first access circuit writes first predetermined data to a first resistive memory cell during a write period and reads a first current passing through the first resistive memory cell after a randomization process. The first calculating circuit calculates the first current to generate a first calculation result. The first certification circuit generates a first password according to the first calculation result.

Abstract: A memory storage apparatus including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of memory cells. The memory cell array is configured to store data. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to apply one of a set signal and a reset signal to a target memory cell among the memory cells to generate a read current. The memory control circuit receives a read current of the target memory cell. The memory control circuit compares the read current with a reference current. The memory control circuit determines whether the target memory cell is failed according to a comparison result. In addition, a method for testing a memory storage apparatus is also provided.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.

Abstract: A high-reliability resistive random access memory (RRAM). A memory cell of a memory cell array is controlled via a word line, a bit line and a source line. The control unit of the RRAM has a word line decoder, a bit line decoder, and a source line decoder and switch circuit. The word line decoder, the bit line decoder and the source line decoder respectively control the voltage applied to the word line, the voltage applied to the bit line, and the voltage applied to the source line. The switch circuit is switched between a first state and a second state to operate the bit line decoder to apply a voltage to the bit line to read the memory cell and to operate the source line decoder to apply a voltage to the source line to read the memory cell alternately.

Abstract: Memory devices are provided. The memory device includes a substrate. A dielectric layer is disposed on the substrate and a plurality of resistive memory cells is disposed on the dielectric layer. Each resistive memory cell includes a via disposed in a first opening of the dielectric layer. A conductive layer is disposed on the via. The memory device further includes a capacitor structure including a bottom electrode, a variable resistance layer disposed on the bottom electrode and a top electrode disposed on the variable resistance layer, wherein the bottom electrode is disposed on the conductive layer.

Abstract: Memory devices are provided. The memory device includes a substrate. A dielectric layer is disposed on the substrate and a plurality of resistive memory cells is disposed on the dielectric layer. Each resistive memory cell includes a via disposed in a first opening of the dielectric layer. A conductive layer is disposed on the via. The memory device further includes a capacitor structure including a bottom electrode, a variable resistance layer disposed on the bottom electrode and a top electrode disposed on the variable resistance layer, wherein the bottom electrode is disposed on the conductive layer.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.

Abstract: The invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate, a capacitor, a protection device, a first metal interconnect, and a second metal interconnect. The capacitor is located on the substrate of a first region. The protection device is located in the substrate of a second region. The capacitor includes a plurality of bottom electrodes, a top electrode, and a capacitor dielectric layer. The top electrode has a first portion and a second portion, wherein the second portion is extended to the second region. The capacitor dielectric layer is located between the bottom electrodes and the top electrode. The first metal interconnect is located between the capacitor and the substrate. The second metal interconnect is located between the second portion of the top electrode and the protection device. The top electrode is electrically connected to the protection device through the second metal interconnect.

Abstract: The invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate, a capacitor, a protection device, a first metal interconnect, and a second metal interconnect. The capacitor is located on the substrate of a first region. The protection device is located in the substrate of a second region. The capacitor includes a plurality of bottom electrodes, a top electrode, and a capacitor dielectric layer. The top electrode has a first portion and a second portion, wherein the second portion is extended to the second region. The capacitor dielectric layer is located between the bottom electrodes and the top electrode. The first metal interconnect is located between the capacitor and the substrate. The second metal interconnect is located between the second portion of the top electrode and the protection device. The top electrode is electrically connected to the protection device through the second metal interconnect.

Abstract: A resistive memory and a repairing method of the resistive memory are provided. Steps of the repairing method includes: operating a plurality of set-reset cycles on the resistive memory; detecting whether the resistive memory encounters an over-set issue after the set-reset cycles are operated; if the resistive memory encounters the over-set issue, executing an enhanced reset programming on the resistive memory. Here, the enhanced reset programming is executed by applying an enhanced reset voltage on the resistive memory during an enhanced reset time period. A product of the enhanced reset voltage and the enhanced reset time period is larger than a product of a reset voltage and a reset time period.

Abstract: A high-reliability resistive random access memory (RRAM). A memory cell of a memory cell array is controlled via a word line, a bit line and a source line. The control unit of the RRAM has a word line decoder, a bit line decoder, and a source line decoder and switch circuit. The word line decoder, the bit line decoder and the source line decoder respectively control the voltage applied to the word line, the voltage applied to the bit line, and the voltage applied to the source line. The switch circuit is switched between a first state and a second state to operate the bit line decoder to apply a voltage to the bit line to read the memory cell and to operate the source line decoder to apply a voltage to the source line to read the memory cell alternately.

Abstract: A resistive memory and a repairing method of the resistive memory are provided. Steps of the repairing method includes: operating a plurality of set-reset cycles on the resistive memory; detecting whether the resistive memory encounters an over-set issue after the set-reset cycles are operated; if the resistive memory encounters the over-set issue, executing an enhanced reset programming on the resistive memory. Here, the enhanced reset programming is executed by applying an enhanced reset voltage on the resistive memory during an enhanced reset time period. A product of the enhanced reset voltage and the enhanced reset time period is larger than a product of a reset voltage and a reset time period.

Abstract: A method includes forming a resistance-switching layer and a second electrode over a first electrode. The method includes applying a forming voltage to the resistance-switching layer such that the resistance of the resistance-switching layer is decreased. The method includes applying an initial reset voltage to the first electrode or the second electrode such that the resistance of the resistance-switching layer is increased. The method includes applying a first set voltage to the first electrode or the second electrode such that the resistance of the resistance-switching layer is decreased. The method includes applying a second reset voltage to first electrode or the second electrode such that the resistance of the resistance-switching layer is increased. The method includes applying a second set voltage to first electrode or the second electrode such that the resistance of the resistance-switching layer is decreased. The second set voltage is lower than the first set voltage.

Abstract: Provided is a resistive random access memory including a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer, wherein the second electrode layer includes a first sublayer, a second sublayer, and a conductive metal oxynitride layer disposed between the first sublayer and the second sublayer.