Patents by Inventor Bo Min Park

Bo Min Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250063717
    Abstract: A method for fabricating a semiconductor device includes forming a stack body by sequentially forming a first layer, a second layer, a third layer, a fourth layer, and a fifth layer over a lower structure; forming an opening in the stack body; forming a capping layer that exposes an edge of the third layer by horizontally recessing the second layer and the fourth layer from the opening; forming a liner structure on the capping layer and an edge of the third layer; forming a sacrificial liner material over the liner structure; recessing the sacrificial liner material and the liner structure to expose an edge of the third layer; forming a third layer pattern by recessing an exposed edge of the third layer; and forming a data storage element that is coupled to the third layer pattern.
    Type: Application
    Filed: February 23, 2024
    Publication date: February 20, 2025
    Inventors: Bo Min PARK, Wan Sup SHIN, Seung Mi YEO
  • Publication number: 20240276741
    Abstract: A semiconductor device according to an embodiment includes a substrate, first and second pillar electrodes extending along a vertical direction substantially perpendicular to a surface of the substrate, and a plurality of memory cells disposed between the first and second pillar electrodes. Each of the plurality of memory cells includes first and second shared device layers that are disposed adjacent to the first and second pillar electrodes, respectively, and extend along the vertical direction, first and second base device layers disposed between the first and second shared device layers, and a control gate electrode disposed on one of the first and second base device layers. Both first and second base device layers are disposed on a plane over the substrate and substantially parallel to the surface of the substrate.
    Type: Application
    Filed: July 20, 2023
    Publication date: August 15, 2024
    Inventors: Bo Min PARK, Seung Wook RYU
  • Patent number: 8975173
    Abstract: A semiconductor device includes buried gates formed over a substrate, storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern, and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jong-Han Shin, Bo-Min Park
  • Patent number: 8921208
    Abstract: A method for fabricating a semiconductor device includes forming a first insulating layer in a first area of the semiconductor substrate, lowering a height of the semiconductor substrate in a second area and a height of the first insulating layer in the first area, selectively forming a sacrificial layer in the second area using the first insulating layer as a growth prevention layer, and forming a first semiconductor layer on the semiconductor substrate including the sacrificial layer.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Seung Beom Baek, Bo Min Park, Young Ho Lee, Jong Chul Lee
  • Publication number: 20140120710
    Abstract: A semiconductor device includes buried gates formed over a substrate, storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern, and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other.
    Type: Application
    Filed: January 7, 2014
    Publication date: May 1, 2014
    Applicant: SK hynix Inc.
    Inventors: Jong-Han SHIN, Bo-Min PARK
  • Publication number: 20120153383
    Abstract: A semiconductor device includes buried gates formed over a substrate, storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern, and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other.
    Type: Application
    Filed: February 16, 2011
    Publication date: June 21, 2012
    Inventors: Jong-Han Shin, Bo-Min Park
  • Publication number: 20090170280
    Abstract: A method of forming isolation layers of a semiconductor device, comprising providing a semiconductor substrate in which a tunnel dielectric layer and a conductive layer are formed in active regions having two ends and trenches are formed in isolation regions; rounding both ends of each active region by performing an O2 plasma process on the semiconductor substrate; forming a first insulating layer on sidewalls of each trench; and, forming a second insulating layer, preferably having a greater fluidity than that of the first insulating layer, on the first insulating layer.
    Type: Application
    Filed: June 27, 2008
    Publication date: July 2, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Bo Min Park
  • Publication number: 20070196997
    Abstract: A method for forming an isolation structure of a semiconductor device includes forming an isolation trench on a semiconductor substrate. A first insulating layer is formed over the isolation trench and the substrate. A spin-on-dielectric (SOD) insulating layer is formed over the first insulation layer, the SOD insulating layer filling the isolation trench and extending above an upper level of the isolation trench. The SOD insulating layer provided within the isolation trench is removed to expose an upper portion of the isolation trench, wherein a lower portion of the isolation trench remains filled with the SOD insulating layer. A second insulating layer is formed over the SOD insulating layer that is filling the lower portion of the isolation trench, wherein the second insulating layer fills the upper portion of the isolation trench.
    Type: Application
    Filed: December 26, 2006
    Publication date: August 23, 2007
    Applicant: Hynix Semiconductor Inc.
    Inventors: Sang Deok Kim, Bo Min Park