Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.

Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.

Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.

Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

Abstract: The present invention relates to a method of image fusion, which uses the brightness difference of the current frame and the previous frame to determine whether the pixel in a frame image is static or dynamic. If the current pixel is static, the previous corresponding pixel is superimposed onto the current pixel; if the current pixel is dynamic, the previous corresponding pixel is replaced with the current pixel.

Abstract: A magnetic tunnel junction memory device includes a vertical stack of magnetic tunnel junction NOR strings located over a substrate. Each magnetic tunnel junction NOR string includes a respective semiconductor material layer that contains a semiconductor source region, a plurality of semiconductor channels, and a plurality of semiconductor drain regions, a plurality of magnetic tunnel junction memory cells having a respective first electrode that is located on a respective one of the plurality of semiconductor drain regions, and a metallic bit line contacting each second electrode of the plurality of magnetic tunnel junction memory cells. The vertical stack of magnetic tunnel junction NOR strings may be repeated along a channel direction to provide a three-dimensional magnetic tunnel junction memory device.

Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.

Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.

Abstract: An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.

Abstract: A dynamic contact management system is provided for analyzing aspects of speech from a customer contact and generating dynamic output based on the analysis. The system can process audio data representing utterances that occur during a customer contact, wherein the processing comprises generating scores based on agent and customer sentiments determined using their respective speech to text data. Based on the processing, the system can generate scores for use in dynamically determining which actions to take, updating displays, analyzing contact outcomes over time, etc.

Abstract: A daily electricity generation planning method of a cascade hydropower plants is disclosed, and the method is comprised of the steps as follows: step 1, regardless of the constraints for opening and closing the generator, taking the power similarity between the power plant group and the typical demand as one of optimization objectives, and performing a first optimization to obtain a daily electricity generation plan; step 2, according to the derived daily electricity generation plan, determining an opening and closing status for the generator; and step 3, considering the constraints for opening and closing the generator, taking the power similarity between the power plant group and the typical demand as the optimization objective, performing a second optimization to obtain the daily electricity generation plan.

Abstract: A tool display device includes a body having a top portion for being hanged on a wall. A mediate portion is connected to the top portion, and a bottom portion is connected to the meditate portion. A cylindrical connection portion is connected to the bottom portion. A slot is defined through the connection portion and extends from the top of the connection portion and ends before the distal end of the connection portion. An opening is defined in the top of the connection portion and communicates with the slot. The slot divides the connection portion into a left part and a right part. The right part has a protrusion extending from the outside thereof. An restriction member is connected between the mediate portion and the right part. A socket is mounted to the connection portion and can only be removed from the connection portion when the restriction member is cut.

Abstract: A tool display device includes a body having a top portion for being hanged on a wall. A mediate portion is connected to the top portion, and a bottom portion is connected to the meditate portion. A cylindrical connection portion is connected to the bottom portion. A slot is defined through the connection portion and extends from the top of the connection portion and ends before the distal end of the connection portion. An opening is defined in the top of the connection portion and communicates with the slot. The slot divides the connection portion into a left part and a right part. The right part has a protrusion extending from the outside thereof. An restriction member is connected between the mediate portion and the right part. A socket is mounted to the connection portion and can only be removed from the connection portion when the restriction member is cut.

Abstract: A blow gun includes a body with first and second paths, a trigger, a control unit, a first spring, a second spring and a first pin. The control unit includes a control member, a bar, a seal ring, an end member, a collar and a fastening member. The control member is received in the first room and has a slot located corresponding to the first hole. The end member is connected to the control member and the seal ring is mounted to the end member to seal the communication between the first and second paths. The first spring is biased between body and the control unit. The second spring is biased between the body and the trigger. The first pin extends through the first hole and is movable in the slot of the control member. The two springs share the force applied thereto to have a long service life.

Abstract: An adaptive universal serial bus (USB) charging method and system are disclosed. In a low-power state, a USB device is charged with a non-USB charging mode. The non-USB charging mode is retained when no variation of a data signal coupled to the USB device is detected. When the data signal possesses variation for a first period, it is switched to a third proprietary charging mode.

Abstract: A printed circuit board includes a first electrically conductive circuit pattern, a substrate layer, an adhesive sheet, and a second electrically conductive circuit pattern, which are arranged in the above described order. The printed circuit board includes a single layer electrically conductive circuit area. The adhesive sheet defines a first opening spatially corresponding to the single layer electrically conductive circuit area. The adhesive sheet includes a first inner sidewall surrounding the first opening. The second electrically conductive circuit pattern defines a second opening spatially corresponding to the single layer electrically conductive circuit area. The second electrically conductive circuit pattern includes a second inner sidewall surrounding the second opening. The first inner sidewall and the second inner sidewall are not completely coplanar.

Abstract: An adaptive universal serial bus (USB) charging method and system are disclosed. In a low-power state, a USB device is charged with a non-USB charging mode. The non-USB charging mode is retained when no variation of a data signal coupled to the USB device is detected. When the data signal possesses variation for a first period, it is switched to a third proprietary charging mode.

Abstract: An adaptive universal serial bus (USB) charging method and system are disclosed. In a low-power state, a USB device is charged with a non-USB charging mode. The non-USB charging mode is retained when no variation of a data signal coupled to the USB device is detected. When the data signal possesses variation for a first period, it is switched to a third proprietary charging mode.

Abstract: A streetlight system includes a plurality of streetlights, disaster warning systems positioned at each of the streetlights and a control center electrically connected with the disaster warning systems. The streetlights are positioned at roadways. Each of the disaster warning systems includes a control system and a broadcasting system. When the control center receives a disaster alert signal, the control center transmits information of disaster shelters and evacuating routes to control system, and the broadcasting system broadcasts information of the disaster shelters and the evacuating routes to people for leading people to escape.