Patents by Inventor Bo Pu
Bo Pu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145691Abstract: The present invention is related to a novel positive electrode active material for lithium-ion battery. The positive electrode active material is expressed by the following formula: Li1.2NixMn0.8-x-yZnyO2, wherein x and y satisfy 0<x?0.8 and 0<y?0.1. In addition, the present invention provides a method of manufacturing the positive electrode active material. The present invention further provides a lithium-ion battery which uses said positive electrode active material.Type: ApplicationFiled: March 14, 2023Publication date: May 2, 2024Inventors: CHUAN-PU LIU, YIN-WEI CHENG, SHIH-AN WANG, BO-LIANG PENG, CHUN-HUNG CHEN, JUN-HAN HUANG, YI-CHANG LI
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Patent number: 11966672Abstract: A method and a system for simulating contact and interaction between a support member and a chamber surrounding rock mass are provided in the application.Type: GrantFiled: July 14, 2023Date of Patent: April 23, 2024Assignee: China University of Mining and TechnologyInventors: Qian Yin, Jiangyu Wu, Hongwen Jing, Zheng Jiang, Tianci Deng, Hai Pu, Qiang Zhang, Bo Meng
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Publication number: 20240130202Abstract: A display panel includes an active area and a peripheral area surrounding the active area, and the display panel further includes: a substrate and a plurality of light emitting devices arranged on the substrate in array, wherein the plurality of light emitting devices are located at least in the active area; a conducting layer comprising a cathode ring and cathodes of the plurality of light emitting devices, wherein the cathode ring is located in the peripheral area, and the cathode ring surrounds the active area; and a lens layer located at a side of the light emitting devices away from the substrate, wherein the lens layer extends from the active area to the peripheral area; wherein an orthographic projection of the lens layer on the substrate is located within an area delineated by an outer contour of an orthographic projection of the cathode ring on the substrate.Type: ApplicationFiled: October 18, 2022Publication date: April 18, 2024Applicants: Yunnan Invensight Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Chao Pu, Shengji Yang, Junyan Yang, Xiaochuan Chen, Kuanta Huang, Pengcheng Lu, Dachao Li, Rongrong Shi, Junbo Wei, Xiao Bai, Bo Yang
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Patent number: 11257741Abstract: A semiconductor package may comprise: a first passivation layer forming an electrical connection with one or more first bumps; a substrate layer including a second passivation layer and a silicon layer; a back-end-of-line (BEOL) layer formed on the substrate layer; and a third passivation layer formed on the BEOL layer forming an electrical connection with one or more second bumps, wherein the substrate layer includes a first signal TSV (Through Silicon Via) which transmits a first signal between the BEOL layer and a first lower pad, a second signal TSV which transmits a second signal between the BEOL layer and a second lower pad, and a ground TSV which is disposed between the first signal TSV and the second signal TSV and formed so that one end thereof is connected to the BEOL layer and the other end thereof floats.Type: GrantFiled: November 22, 2019Date of Patent: February 22, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Bo Pu, Jun So Pak, Sung Wook Moon
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Patent number: 11205614Abstract: A stack package may include a first substrate package, a second substrate package, an interposer and at least one semiconductor chip. The first substrate package may include a plurality of first pads isolated from direct contact with each other by a first pitch. The second substrate package may be under the first substrate package. The second substrate package may include a plurality of second pads isolated from direct contact with each other by a second pitch. The second pitch may be different from the first pitch. The interposer may be above the first substrate package. The interposer may include a plurality of third pads isolated from direct contact with each other by a third pitch. The semiconductor chip may be arranged above the interposer.Type: GrantFiled: April 30, 2020Date of Patent: December 21, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jun So Pak, Seungki Nam, Jiyoung Park, Bo Pu
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Patent number: 11080460Abstract: A method of modeling a high speed channel in a semiconductor package, the high speed channel including a plurality of first connection wirings on an upper surface of a semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate, includes: receiving design information of the high speed channel, dividing the design information into a first layout including the plurality of first connection wirings and a second layout including the plurality of through electrodes; performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool; performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout; and obtaining an integrated modeling result of an entirety of the high speed channel by combining results of the first and second modeling operations.Type: GrantFiled: August 6, 2020Date of Patent: August 3, 2021Inventors: Bo Pu, Jun So Pak
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Publication number: 20210110096Abstract: A method of modeling a high speed channel in a semiconductor package, the high speed channel including a plurality of first connection wirings on an upper surface of a semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate, includes: receiving design information of the high speed channel, dividing the design information into a first layout including the plurality of first connection wirings and a second layout including the plurality of through electrodes; performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool; performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout; and obtaining an integrated modeling result of an entirety of the high speed channel by combining results of the first and second modeling operations.Type: ApplicationFiled: August 6, 2020Publication date: April 15, 2021Inventors: Bo Pu, Jun So Pak
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Publication number: 20210028100Abstract: A stack package may include a first substrate package, a second substrate package, an interposer and at least one semiconductor chip. The first substrate package may include a plurality of first pads isolated from direct contact with each other by a first pitch. The second substrate package may be under the first substrate package. The second substrate package may include a plurality of second pads isolated from direct contact with each other by a second pitch. The second pitch may be different from the first pitch. The interposer may be above the first substrate package. The interposer may include a plurality of third pads isolated from direct contact with each other by a third pitch. The semiconductor chip may be arranged above the interposer.Type: ApplicationFiled: April 30, 2020Publication date: January 28, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Junso PAK, Seungki NAM, Jiyoung PARK, Bo PU
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Publication number: 20200381347Abstract: A semiconductor package may comprise: a first passivation layer forming an electrical connection with one or more first bumps; a substrate layer including a second passivation layer and a silicon layer; a back-end-of-line (BEOL) layer formed on the substrate layer; and a third passivation layer formed on the BEOL layer forming an electrical connection with one or more second bumps, wherein the substrate layer includes a first signal TSV (Through Silicon Via) which transmits a first signal between the BEOL layer and a first lower pad, a second signal TSV which transmits a second signal between the BEOL layer and a second lower pad, and a ground TSV which is disposed between the first signal TSV and the second signal TSV and formed so that one end thereof is connected to the BEOL layer and the other end thereof floats.Type: ApplicationFiled: November 22, 2019Publication date: December 3, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Bo PU, Jun So PAK, Sung Wook MOON
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Patent number: 10625968Abstract: A media diversion apparatus for a printing system is described. In an example implementation, the apparatus comprises a media diverter to route media printed by a print assembly of a printing system. The media diverter, in a first position, is to route cut-sheet media from the print assembly to a first output region. The media diverter, in a second position, is to route roll media from the print assembly to a second output region.Type: GrantFiled: June 29, 2016Date of Patent: April 21, 2020Assignee: Hewlett-Packard Development Company, L.P.Inventors: Xiaoxi Huang, Bo Pu, Ah Chong Tee
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Publication number: 20190135568Abstract: A media diversion apparatus for a printing system is described. In an example implementation, the apparatus comprises a media diverter to route media printed by a print assembly of a printing system. The media diverter, in a first position, is to route cut-sheet media from the print assembly to a first output region. The media diverter, in a second position, is to route roll media from the print assembly to a second output region.Type: ApplicationFiled: June 29, 2016Publication date: May 9, 2019Applicant: Hewlett-Packard Development Company, L.P.Inventors: Xiaoxi Huang, Bo Pu, Ah Chong Tee