Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.

Abstract: A semiconductor memory device includes a first dielectric wall, a second dielectric wall, first channel portions, second channel portions, an isolation wall, and a dielectric feature. The second dielectric wall is spaced apart from the first dielectric wall in a first direction. The first channel portions are disposed on a side of the first dielectric wall and are spaced apart from each other in a second direction transverse to the first direction. The second channel portions are disposed on a side of the second dielectric wall and are spaced apart from each other in the second direction. The isolation wall is located between the first dielectric wall and the second dielectric wall. The dielectric feature is disposed to separate the first dielectric wall and the isolation wall, and is disposed on the other side of the first dielectric wall opposite to the first channel portions in the first direction.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming first, second and third fin structures over a substrate, forming a first dielectric material along a first trench between the first fin structure and the second fin structure and along a second trench between the second fin structure and the third fin structure, removing a first portion of the first dielectric material along the second trench while leaving a second portion of the first dielectric material along the first trench as a dielectric liner, depositing a second dielectric material over the dielectric liner and filling the first trench and the second trench, and etching back the second dielectric material until the dielectric liner is exposed. A first portion of the second dielectric material remaining in the first trench forms a dielectric wall.

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result.

Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a plurality of page buffers, storing an input data; a plurality of memory planes coupled to the page buffers, based on received addresses of the memory planes, a plurality of weights stored in the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result.

Abstract: An integrated circuit includes a transistor having a plurality of semiconductor nanostructures arranged in a stack and corresponding to channel regions of the transistor. The transistor includes a source/drain region in contact with the channel regions. The transistor includes a silicide that extends downward along a side of the source/drain region.

Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

Abstract: A semiconductor device includes a substrate and a transistor. The transistor includes a first channel region overlying the substrate and a source/drain region in contact with the first channel region. The source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region.

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a plurality of page buffers, storing an input data; a plurality of memory planes coupled to the page buffers, based on received addresses of the memory planes, a plurality of weights stored in the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result.

Abstract: A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.

Abstract: A capacitance-type sensing system for indirect contact includes a capacitance-type sensor and a grounding conductor. The capacitance-type sensor includes a sensing electrode and a driving circuit electrically connected to the sensing electrode. The driving circuit has a grounding terminal. The grounding conductor is electrically connected to the grounding terminal and configured to contact a grounding surface. A contact area of the grounding conductor is greater than or equal to 3000 mm2.

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result.

Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results, wherein in performing bitwise multiplication, the memory cells generate a plurality of memory cell currents; a digital accumulating circuit for performing a digital accumulating on the multiplication results; an analog accumulating circuit for performing an analog accumulating on the memory cell currents to generate a first MAC operation result; and a decision unit for deciding whether to perform the analog accumulating; the digital accumulating or a hybrid accumulating, wherein in performing the hybrid accumulating, whether the digital accumulating circuit is triggered is based on the first MAC operation result.

Abstract: A capacitance-type sensing system for indirect contact includes a capacitance-type sensor and a grounding conductor. The capacitance-type sensor includes a sensing electrode and a driving circuit electrically connected to the sensing electrode. The driving circuit has a grounding terminal. The grounding conductor is electrically connected to the grounding terminal and configured to contact a grounding surface. A contact area of the grounding conductor is greater than or equal to 3000 mm2.

Abstract: A touch panel with electromagnetic induction function comprising a light-emitting diode backlight layer, an electromagnetic antenna, a display panel layer, a touch panel layer and a protective layer. The light emitting diode backlight layer has a plurality of light emitting diode units. The electromagnetic antenna is disposed on the backlight layer for emitting an alternating electromagnetic field and receiving a resonance signal. The display panel layer is disposed on the backlight layer. The touch panel layer is disposed on the display panel layer for capacitive touch. The protective layer is disposed on the touch panel layer to protect the touch panel layer. An electromagnetic pen for electromagnetic touch is configured to receive the alternating electromagnetic field and then emit the resonance signal.

Abstract: A touch panel with electromagnetic induction function comprising a light-emitting diode backlight layer, an electromagnetic antenna, a display panel layer, a touch panel layer and a protective layer. The light emitting diode backlight layer has a plurality of light emitting diode units. The electromagnetic antenna is disposed on the backlight layer for emitting an alternating electromagnetic field and receiving a resonance signal. The display panel layer is disposed on the backlight layer. The touch panel layer is disposed on the display panel layer for capacitive touch. The protective layer is disposed on the touch panel layer to protect the touch panel layer. An electromagnetic pen for electromagnetic touch is configured to receive the alternating electromagnetic field and then emit the resonance signal.

Abstract: A touch device in spherical or other curved form includes a hollow spherical casing and at least one touch sensing layer. The spherical casing includes an inner surface and an outer surface, the touch sensing layer is attached to the inner surface of the spherical casing, the touch sensing layer includes a core portion and a touch portion. The touch portion extends and diverges outwardly from the core portion. The touch portion comprises a plurality of sub-touch portions, an area of each sub-touch portion is greater than an area of the core portion. The disclosure also includes a curved non-spherical touch device.