Patents by Inventor Bo-Shian Hsu

Bo-Shian Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10671313
    Abstract: A data storage apparatus includes a cache memory module and a NAND flash memory module including a cache memory mirror and a user data storage zone. The cache memory module is connected to the cache memory mirror via a path and electrically connected to the user data storage zone via another path. The cache memory module receives a write command that includes user data from a host, writes a copy of the user data into the user data storage zone in a write-back mode, and writes another copy of the user data cache memory mirror in a write-through mode. If some of the user data are lost from the cache memory module before they are written into the user data storage zone, the user data written in the cache memory mirror are copied and written into the cache memory module when the data storage apparatus is initiated again.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: June 2, 2020
    Assignee: GOKE US RESEARCH LABORATORY
    Inventors: Kun-Lung Hsieh, Bo-Shian Hsu, Po-Chien Chang
  • Patent number: 10489291
    Abstract: A data storage apparatus executes a garbage collection method. The data storage apparatus includes a NAND flash memory including blocks each of which includes pages. In the garbage collection method, a destination block is selected from the blocks. Mapping tables and a relevance bitmap are built before writing user data into the destination block. Each bit in the relevance bitmap is related to one of the mapping tables. A victim block is selected from the blocks. At least one of the mapping tables are read according to the relevance bitmap for the victim block. It is determined whether the pages, one after another, of the victim block are in the read mapping tables. The page is set to be a valid page if a page of the victim block is in a read mapping table. Data in the valid pages is written into another block.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: November 26, 2019
    Assignee: Goke US Research Laboratory
    Inventors: Yen-Lan Hsu, Bo-Shian Hsu, Po-Chien Chang
  • Publication number: 20190227618
    Abstract: A data storage apparatus includes a NAND flash memory, an external memory and two cores. The external memory includes a first portion and a second portion smaller than the first portion. Each of the cores includes a CPU, an ITCM and a DTCM. The data storage apparatus is switchable between an operative state and hibernation. In the hibernation, the NAND flash memory, the first portion of the external memory, the CPU of the first core, and the CPU, ITCM and DTCM of the second core are shut down while the second portion of the external memory and the ITCM and DTCM of the first core are kept awake.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 25, 2019
    Inventors: Yung-Tzu Huang, Bo-Shian Hsu, Po-Chien Chang
  • Publication number: 20190227925
    Abstract: A data storage apparatus executes a garbage collection method. The data storage apparatus includes a NAND flash memory including blocks each of which includes pages. In the garbage collection method, a destination block is selected from the blocks. Mapping tables and a relevance bitmap are built before writing user data into the destination block. Each bit in the relevance bitmap is related to one of the mapping tables. A victim block is selected from the blocks. Some of the mapping tables are read according to the relevance bitmap for the victim block. It is determined whether if the pages, one after another, of the victim block are in the read mapping tables. The page is set to be a valid page if a page of the victim block is in a read mapping table. Data in the valid pages is written into another block.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 25, 2019
    Inventors: Yen-Lan Hsu, Bo-Shian Hsu, Po-Chien Chang
  • Publication number: 20190227708
    Abstract: A data storage apparatus includes a cache memory module and a NAND flash memory module including a cache memory mirror and a user data storage zone. The cache memory module is connected to the cache memory mirror via a path and electrically connected to the user data storage zone via another path. The cache memory module receives a write command that includes user data from a host, writes a copy of the user data into the user data storage zone in a write-back mode, and writes another copy of the user data cache memory mirror in a write-through mode. If some of the user data are lost from the cache memory module before they are written into the user data storage zone, the user data written in the cache memory mirror are copied and written into the cache memory module when the data storage apparatus is initiated again.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 25, 2019
    Inventors: Kun-Lung Hsieh, Bo-Shian Hsu, Po-Chien Chang
  • Publication number: 20190228827
    Abstract: A method for dynamically managing a NAND flash memory includes the step of receiving a write command from a host. The write command includes data to be stored in the NAND flash memory. Then, it is determined whether if the NAND flash memory has passed an early phase of its life of service. A first portion of the NAND flash memory is allocated to be an SLC cache memory if the NAND flash memory is in the early phase of its life of service. A second portion of the NAND flash memory is allocated to be the SLC cache memory if the NAND flash memory is not in the early phase of its life of service. The second portion is smaller than the first portion. Finally, the data is written into the SLC cache memory according to the write command.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 25, 2019
    Inventors: Jia-Jyun Syu, Bo-Shian Hsu, Po-Chien Chang