Patents by Inventor Bo-Shiang Fang
Bo-Shiang Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170271251Abstract: A semiconductor substrate is disclosed. The semiconductor substrate includes a substrate body having at least an opening formed on a surface thereof, wherein the surface of the substrate body and a wall of the opening are made of an insulating material; and a circuit layer formed on the surface of the substrate body, wherein the circuit layer covers an end of the opening and is electrically insulated from the opening. The opening facilitates to increase the thickness of the insulating structure between the circuit layer and the substrate body of a silicon material to prevent signal degradation when high frequency signals are applied to the circuit layer.Type: ApplicationFiled: June 2, 2017Publication date: September 21, 2017Inventors: Bo-Shiang Fang, Ho-Chuan Lin, Chia-Chu Lai, Min-Han Chuang, Li-Fang Lin
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Patent number: 9698090Abstract: A semiconductor substrate is disclosed. The semiconductor substrate includes a substrate body having at least an opening formed on a surface thereof, wherein the surface of the substrate body and a wall of the opening are made of an insulating material; and a circuit layer formed on the surface of the substrate body, wherein the circuit layer covers an end of the opening and is electrically insulated from the opening. The opening facilitates to increase the thickness of the insulating structure between the circuit layer and the substrate body of a silicon material to prevent signal degradation when high frequency signals are applied to the circuit layer.Type: GrantFiled: January 30, 2013Date of Patent: July 4, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Bo-Shiang Fang, Ho-Chuan Lin, Chia-Chu Lai, Min-Han Chuang, Li-Fang Lin
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Patent number: 9503043Abstract: A duplexer is provided, which includes a first, a second and a third signal ports; a first filter and a second filter. The first filter has first, second, and third resonant circuits that have first, second and third inductors, respectively. The first, second and third inductors are mutually inductive. The first and third resonant circuits are electrically connected to the first and second signal ports, respectively. The second filter has fourth, fifth and sixth resonant circuits that have fourth, fifth and sixth inductors, respectively. The fourth resonant circuit is connected in series with the first resonant circuit. The fifth inductor and the fourth inductor are mutually inductive. The sixth resonant circuit is electrically connected to the third signal port. The second filter further has a main capacitor connected in series with the fifth and sixth resonant circuits respectively and located therebetween.Type: GrantFiled: May 2, 2013Date of Patent: November 22, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Min-Han Chuang, Chia-Chu Lai, Bo-Shiang Fang, Ho-Chuan Lin, Yen-Yu Chen
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Patent number: 9281557Abstract: A multi bandwidth balun is provided, including a main signal port, a main inductor electrically connected to the main signal port, a first inductor inducted mutually with the main inductor to constitute a first inductor of a first conversion circuit, a first capacitor module connected in parallel to the first conversion circuit, two first signal ports electrically connected to the first capacitor module, a first main capacitor electrically connected to the first signal port and the first capacitor module therebetween, a second inductor inducted mutually with the main inductor to constitute a second inductor of a second conversion circuit, a second capacitor module connected in parallel to the second conversion circuit, two second signal ports electrically connected to the second capacitor module, and a second main capacitor electrically connected to the second signal port and the second capacitor module therebetween.Type: GrantFiled: November 26, 2013Date of Patent: March 8, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chia-Chu Lai, Min-Han Chuang, Bo-Shiang Fang, Ho-Chuan Lin, Li-Fang Lin
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Patent number: 9196941Abstract: A cross-coupled bandpass filter includes first, second, third and fourth resonators such that magnetic couplings are generated between the first and second resonators, between the third and fourth resonators and between the first and fourth resonators, a capacitive coupling is generated between the second and third resonators, and the magnetic coupling between the first and fourth resonators has a polarity opposite to that of the capacitive coupling between the second and third resonators, thereby generating two transmission zeros in a transmission rejection band.Type: GrantFiled: March 30, 2012Date of Patent: November 24, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Min-Han Chuang, Chia-Chu Lai, Bo-Shiang Fang, Ho-Chuan Lin, Sung-Chun Wu
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Patent number: 9054670Abstract: A cross-coupled bandpass filter includes first, second and third resonators such that a positive mutual inductance is generated between the first and third resonators and mutual inductance generated between the first and second resonators and mutual inductance generated between the second and third resonators have the same polarity, thereby generating a transmission zero in a high frequency rejection band.Type: GrantFiled: August 17, 2012Date of Patent: June 9, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Min-Han Chuang, Chia-Chu Lai, Bo-Shiang Fang, Ho-Chuan Lin, Li-Fang Lin
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Publication number: 20140320374Abstract: A multi bandwidth balun is provided, including a main signal port, a main inductor electrically connected to the main signal port, a first inductor inducted mutually with the main inductor to constitute a first inductor of a first conversion circuit, a first capacitor module connected in parallel to the first conversion circuit, two first signal ports electrically connected to the first capacitor module, a first main capacitor electrically connected to the first signal port and the first capacitor module therebetween, a second inductor inducted mutually with the main inductor to constitute a second inductor of a second conversion circuit, a second capacitor module connected in parallel to the second conversion circuit, two second signal ports electrically connected to the second capacitor module, and a second main capacitor electrically connected to the second signal port and the second capacitor module therebetween.Type: ApplicationFiled: November 26, 2013Publication date: October 30, 2014Applicant: Siliconware Precision Industries Co., LtdInventors: Chia-Chu Lai, Min-Han Chuang, Bo-Shiang Fang, Ho-Chuan Lin, Li-Fang Lin
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Publication number: 20140204806Abstract: A duplexer is provided, which includes a first, a second and a third signal ports; a first filter and a second filter. The first filter has first, second, and third resonant circuits that have first, second and third inductors, respectively. The first, second and third inductors are mutually inductive. The first and third resonant circuits are electrically connected to the first and second signal ports, respectively. The second filter has fourth, fifth and sixth resonant circuits that have fourth, fifth and sixth inductors, respectively. The fourth resonant circuit is connected in series with the first resonant circuit. The fifth inductor and the fourth inductor are mutually inductive. The sixth resonant circuit is electrically connected to the third signal port. The second filter further has a main capacitor connected in series with the fifth and sixth resonant circuits respectively and located therebetween.Type: ApplicationFiled: May 2, 2013Publication date: July 24, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Min-Han Chuang, Chia-Chu Lai, Bo-Shiang Fang, Ho-Chuan Lin, Yen-Yu Chen
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Publication number: 20140184261Abstract: A testing method is provided, including providing a testing apparatus including a carrier member and a testing element, the carrier member comprising a first surface, a second surface opposing the first surface, and an elastic conductive area defined on the first surface; disposing an object-to-be-tested on the elastic conductive area; electrically connecting the testing element to the object-to-be-tested and the carrier member, to form an electric loop among the carrier member, the object-to-be-tested and the testing element. Through the design of the elastic conductive area, the object-to-be-tested can be secured with a small pressure applied thereto, and is prevented from being cracked.Type: ApplicationFiled: October 17, 2013Publication date: July 3, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chia-Chu Lai, Ming-Fan Tsai, Ho-Chuan Lin, Min-Han Chuang, Bo-Shiang Fang
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Patent number: 8736059Abstract: An interconnecting mechanism is provide, which includes paired first sub-interconnecting mechanisms and paired second sub-interconnecting mechanisms. The first pair of sub-interconnecting mechanisms includes first and second axially symmetrical spiral conductive elements. The second pair of sub-interconnecting mechanisms includes third and fourth axially symmetrical spiral conductive elements. Configuring the pairs of sub-interconnecting mechanisms in a differential transmission structure having a spiral shape is used to avert sounds and noise signals between different chips or substrates caused by a miniaturizing fabrication process or an increased wiring density.Type: GrantFiled: November 29, 2011Date of Patent: May 27, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ming-Fan Tsai, Hsin-Hung Lee, Bo-Shiang Fang, Li-Fang Lin
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Publication number: 20140124950Abstract: A semiconductor substrate is disclosed. The semiconductor substrate includes a substrate body having at least an opening formed on a surface thereof, wherein the surface of the substrate body and a wall of the opening are made of an insulating material; and a circuit layer formed on the surface of the substrate body, wherein the circuit layer covers an end of the opening and is electrically insulated from the opening. The opening facilitates to increase the thickness of the insulating structure between the circuit layer and the substrate body of a silicon material to prevent signal degradation when high frequency signals are applied to the circuit layer.Type: ApplicationFiled: January 30, 2013Publication date: May 8, 2014Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Bo-Shiang Fang, Ho-Chuan Lin, Chia-Chu Lai, Min-Han Chuang, Li-Fang Lin
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Patent number: 8493168Abstract: An asymmetric differential inductor includes first and second conductive wirings spirally disposed on a substrate having a first input terminal, a second input terminal, a ground terminal, and a central conductive wiring. The central conductive wiring has a central contact connecting the ground terminal and a central end away from the ground terminal. The first conductive wiring extends across the central conductive wiring and has a first contact connecting the first input terminal and a first end connecting the central end. The second conductive wiring extends across the central conductive wiring and interlaces with the first conductive wiring and has a second contact connecting the second input terminal and a second end connecting the central end. Corresponding portions of wiring sections of the first and second conductive wirings at opposite sides of the central conductive wiring are asymmetrical to one another to thereby save substrate space and facilitate circuit layout.Type: GrantFiled: August 31, 2011Date of Patent: July 23, 2013Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ming-Fan Tsai, Kuan-Yu Chen, Bo-Shiang Fang, Hsin-Hung Lee
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Publication number: 20130154765Abstract: A cross-coupled bandpass filter includes first, second, third and fourth resonators such that magnetic couplings are generated between the first and second resonators, between the third and fourth resonators and between the first and fourth resonators, a capacitive coupling is generated between the second and third resonators, and the magnetic coupling between the first and fourth resonators has a polarity opposite to that of the capacitive coupling between the second and third resonators, thereby generating two transmission zeros in a transmission rejection band.Type: ApplicationFiled: March 30, 2012Publication date: June 20, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Min-Han Chuang, Chia-Chu Lai, Bo-Shiang Fang, Ho-Chuan Lin, Sung-Chun Wu
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Publication number: 20130141187Abstract: A cross-coupled bandpass filter includes first, second and third resonators such that a positive mutual inductance is generated between the first and third resonators and mutual inductance generated between the first and second resonators and mutual inductance generated between the second and third resonators have the same polarity, thereby generating a transmission zero in a high frequency rejection band.Type: ApplicationFiled: August 17, 2012Publication date: June 6, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Min-Han Chuang, Chia-Chu Lai, Bo-Shiang Fang, Ho-Chuan Lin, Li-Fang Lin
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Patent number: 8399965Abstract: A layer structure with an electromagnetic interference (EMI) shielding effect is applicable for reducing an EMI effect caused by signal transmission between through silicon vias, so as to effectively provide the EMI shielding effect between electrical interconnections of a three-dimensional (3D) integrated circuit. By forming EMI-shielding through silicon vias at predetermined positions between the through silicon vias used for signal transmission, a good EMI shielding effect can be attended, and signal distortion possibly caused by the EMI effect can be reduced between different chips or substrates.Type: GrantFiled: September 23, 2011Date of Patent: March 19, 2013Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ming-Fan Tsai, Hsin-Hung Lee, Bo-Shiang Fang
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Publication number: 20130032931Abstract: A layer structure with an electromagnetic interference (EMI) shielding effect is applicable for reducing an EMI effect caused by signal transmission between through silicon vias, so as to effectively provide the EMI shielding effect between electrical interconnections of a three-dimensional (3D) integrated circuit. By forming EMI-shielding through silicon vias at predetermined positions between the through silicon vias used for signal transmission, a good EMI shielding effect can be attended, and signal distortion possibly caused by the EMI effect can be reduced between different chips or substrates.Type: ApplicationFiled: September 23, 2011Publication date: February 7, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Ming-Fan Tsai, Hsin-Hung Lee, Bo-Shiang Fang
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Publication number: 20130034971Abstract: An interconnecting mechanism is provide, which includes paired first sub-interconnecting mechanisms and paired second sub-interconnecting mechanisms. The first pair of sub-interconnecting mechanisms includes first and second axially symmetrical spiral conductive elements. The second pair of sub-interconnecting mechanisms includes third and fourth axially symmetrical spiral conductive elements. Configuring the pairs of sub-interconnecting mechanisms in a differential transmission structure having a spiral shape is used to avert sounds and noise signals between different chips or substrates caused by a miniaturizing fabrication process or an increased wiring density.Type: ApplicationFiled: November 29, 2011Publication date: February 7, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Ming-Fan Tsai, Hsin-Hung Lee, Bo-Shiang Fang, Li-Fang Lin
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Publication number: 20120299683Abstract: An asymmetric differential inductor includes first and second conductive wirings spirally disposed on a substrate having a first input terminal, a second input terminal, a ground terminal, and a central conductive wiring. The central conductive wiring has a central contact connecting the ground terminal and a central end away from the ground terminal. The first conductive wiring extends across the central conductive wiring and has a first contact connecting the first input terminal and a first end connecting the central end. The second conductive wiring extends across the central conductive wiring and interlaces with the first conductive wiring and has a second contact connecting the second input terminal and a second end connecting the central end. Corresponding portions of wiring sections of the first and second conductive wirings at opposite sides of the central conductive wiring are asymmetrical to one another to thereby save substrate space and facilitate circuit layout.Type: ApplicationFiled: August 31, 2011Publication date: November 29, 2012Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Ming-Fan Tsai, Kuan-Yu Chen, Bo-Shiang Fang, Hsin-Hung Lee
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Publication number: 20120299682Abstract: A symmetric differential inductor structure includes first, second, third and fourth spiral conductive wirings disposed in four quadrants of a substrate, respectively. Further, a fifth conductive wiring connects the first and fourth spiral conductive wirings, and a sixth conductive wiring connects the second and third spiral conductive wirings. The first and second spiral conductive wirings are symmetric but not intersected with one another, and the third and fourth spiral conductive wirings are symmetric but not intersected with one another. Therefore, the invention attains full geometric symmetry to avoid using conductive wirings that occupy a large area of the substrate as in the prior art and to thereby increase the product profit and yield.Type: ApplicationFiled: September 23, 2011Publication date: November 29, 2012Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Ming-Fan Tsai, Kuan-Yu Chen, Bo-Shiang Fang, Hsin-Hung Lee
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Patent number: 8305182Abstract: A symmetric differential inductor structure includes first, second, third and fourth spiral conductive wirings disposed in four quadrants of a substrate, respectively. Further, a fifth conductive wiring connects the first and fourth spiral conductive wirings, and a sixth conductive wiring connects the second and third spiral conductive wirings. The first and second spiral conductive wirings are symmetric but not intersected with one another, and the third and fourth spiral conductive wirings are symmetric but not intersected with one another. Therefore, the invention attains full geometric symmetry to avoid using conductive wirings that occupy a large area of the substrate as in the prior art and to thereby increase the product profit and yield.Type: GrantFiled: September 23, 2011Date of Patent: November 6, 2012Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ming-Fan Tsai, Kuan-Yu Chen, Bo-Shiang Fang, Hsin-Hung Lee