Abstract: A multiplexer circuit, of power supply (PS) voltages, includes: finger circuits correspond to the PS voltages, each selectable finger circuit (A) having an input node which is finger-circuit-specific and an output node which is common to the finger circuits, (B) including an anti-leak transistor of a first conductivity (C1) type, a selector transistor and a driver transistor transistors of a second conductivity (C2) type connected in series between the input node and the output node, and (C) being configured to receive a corresponding one of the PS voltages from the input node, and provide, if selected, a first version of the corresponding PS voltage to the output node.

Abstract: The present invention provides a drum with a lug mechanism, which can adjust the tension of a drumhead mounted on the drum. The lug mechanism can also prevent loosening of a tension-adjusting member of the lug mechanism and enhance resonance of the drum.

Abstract: The present invention provides a drum with a lug mechanism, which can adjust the tension of a drumhead mounted on the drum. The lug mechanism can also prevent loosening of a tension-adjusting member of the lug mechanism and enhance resonance of the drum.

Abstract: An electrostatic discharge (ESD) protection circuit (for a protected device in a semiconductor system, the protected device being coupled between a first node and a first reference voltage) includes: an ESD device coupled between the first node and the first reference voltage; a logic block including a first input and an output, the first input being coupled to a second reference voltage, and the output being coupled to an input of the ESD device and a feedback control circuit coupled between the first node and a second input of the logic block.

Abstract: A supporting leg to support a drum includes a first rod, a second rod, and a third rod. A first angle-adjusting mechanism is provided between the first rod and the second rod to adjust a first angle between the first rod and the second rod. A second angle-adjusting mechanism is provided between the second rod and the third rod to adjust a second angle between the second rod and the third rod. The output sound of the drum can be adjusted by changing the first angle and the second angle.

Abstract: A multi-purpose drum that can be assembled into a floor-tom, a bass drum, or a gong bass drum through different mating parts according to the performance requirements. This multi-purpose drum is lightweight, easy to carry, and quick to assemble.

Abstract: A multiplexer circuit, of power supply (PS) voltages, includes: finger circuits correspond to the PS voltages, each selectable finger circuit (A) having an input node which is finger-circuit-specific and an output node which is common to the finger circuits, (B) including an anti-leak transistor of a first conductivity (C1) type, a selector transistor and a driver transistor transistors of a second conductivity (C2) type connected in series between the input node and the output node, and (C) being configured to receive a corresponding one of the PS voltages from the input node, and provide, if selected, a first version of the corresponding PS voltage to the output node.

Abstract: A multiplexer circuit, of power supply (PS) voltages, includes: selectable finger circuits corresponding to the PS voltages, each selectable finger circuit: having an input node which is finger-circuit-specific and an output node which is common to the finger circuits; being configured to receive a corresponding one of the PS voltages from the input node and, if selected, provide a first version of the corresponding PS voltage to the output node. Each of the selectable finger circuits includes: a non-enhancement mode transistor of a first conductivity (C1) type (C1-type transistor) and enhancement mode first and second transistors of a second conductivity (C2) type (C2-type transistor) connected in series between the input node and the output node.

Abstract: A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode.

Abstract: A circuit device includes core circuitry. The circuit device further includes a guard ring surrounding the core circuitry. The guard ring includes a first plurality of fin structures arranged in a first direction parallel to a first side of the core circuitry, wherein adjacent fin structures of the first plurality of fin structures are separated by a first distance. The guard ring further includes a second plurality of fin structures arranged in a second direction parallel to a second side of the core circuitry, wherein adjacent fin structures of the second plurality of fin structures are separated by a second distance, and the second distance is smaller than the first distance.

Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter, and configured for driving the input/output pad to a voltage level based on the data signal and the output enable signal.

Abstract: A multiplexer circuit, of power supply (PS) voltages, includes: selectable finger circuits corresponding to the PS voltages, each selectable finger circuit: having an input node which is finger-circuit-specific and an output node which is common to the finger circuits; being configured to receive a corresponding one of the PS voltages from the input node and, if selected, provide a first version of the corresponding PS voltage to the output node. Each of the selectable finger circuits includes: a non-enhancement mode transistor of a first conductivity (C1) type (C1-type transistor) and enhancement mode first and second transistors of a second conductivity (C2) type (C2-type transistor) connected in series between the input node and the output node.

Abstract: A method of making a circuit device includes forming core circuitry. The core circuitry includes a doped region in the core circuit. The method further includes implanting a first set of guard rings around a periphery of the core circuitry. The first set of guard rings has a first dopant type. Implanting the first set of guard rings includes implanting the first set of guard rings spaced from the doped region. The method further includes implanting a second set of guard rings having a second dopant type, wherein the second dopant type being opposite to the first dopant type. At least one guard ring of the second set of guard rings is around a periphery of at least one guard ring of the first set of guard rings.

Abstract: A method comprises forming an active region including a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by an isolation region, depositing an epitaxial growth block layer over the active region, patterning the epitaxial growth block layer to define a first growth area and a second growth area and growing an N+ region in the first growth area and a P+ region in the second growth area.

Abstract: In some embodiments, a field effect transistor structure includes a substrate, a fin structure and a gate structure. The fin structure is formed over the substrate. The fin structure includes a first channel region, a first source or drain region and a second source or drain region. The first source or drain region and the second source or drain region are formed on opposite ends of the first channel region, respectively. The well region is formed of the same conductivity type as the second source or drain region, connected to the second source or drain region, and extended to the substrate. The first gate structure wraps around the first channel region in the fin structure.

Abstract: A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.

Abstract: A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.

Abstract: An integrated circuit including a first level shifter configured to receive a first input signal and a first power supply signal, and to output a first output signal. The integrated circuit further includes a first inverter configured to receive the first output signal, and to output a first inverter signal. The integrated circuit further includes a second level shifter configured to receive a second input signal and a second power supply signal, and to output a second output signal, wherein a voltage level of the second power supply signal is different from a voltage level of the first power supply signal. The integrated circuit further includes a second inverter configure to receive the second output signal, and to output a second inverter signal. The integrated circuit further includes an output buffer configured to receive the first inverter signal and the second inverter signal, and to output a buffer output signal.

Abstract: A semiconductor device is provided. The semiconductor device includes a first conductive portion on a first side of a first shallow trench isolation (STI) region. The first conductive portion is formed within a first well having a first conductivity type. The first conductive portion has the first conductivity type. The first conductive portion is connected to an electro static discharge (ESD) circuit. A second conductive portion is on a second side of the first STI region. The second conductive portion is formed within a second well having a second conductivity type. The second conductive portion having the first conductivity type is connected to a first nanowire and an input output I/O port.

Abstract: A semiconductor device is provided. The semiconductor device includes a first transistor on a first side of a shallow trench isolation (STI) region and a second transistor on a second side of the STI region. The first transistor includes a first conductive portion having a second conductivity type formed within a well having a first conductivity type, a first nanowire connected to the first conductive portion and a first active area, and a first gate surrounding the first nanowire. The second transistor includes a second conductive portion having the second conductivity type formed within the well, a second nanowire connected to the second conductive portion and a second active area, and a second gate surrounding the second nanowire. Excess current from an ESD event travels through the first conductive portion through the well to the second conductive portion bypassing the first nanowire and the second nanowire.