Patents by Inventor Bo-Ting Lin
Bo-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11966077Abstract: A light emission apparatus includes a laser diode configured to emit a light; a laser driver electrically coupled to the laser diode, the laser driver being configured to drive the laser diode to generate the light; and an optical module arranged to receive the light emitted by the laser diode, the optical module comprising at least one optical element and being configured to adjust the light and emits a transmitting light; wherein the transmitting light emits from the optical module with an illumination angle and the optical module adjusts the light to vary the illumination angle.Type: GrantFiled: July 8, 2019Date of Patent: April 23, 2024Assignee: Artilux, Inc.Inventors: Yun-Chung Na, Chien-Lung Chen, Chieh-Ting Lin, Yu-Yi Hsu, Hui-Wen Chen, Bo-Jiun Chen, Shih-Tai Chuang
-
Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
-
Patent number: 11916548Abstract: A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, an inverter, and a resistor-capacitor (RC) circuit coupled in series with the inverter between the input terminal and the output terminal. The RC circuit includes an NMOS transistor coupled between an RC circuit output terminal and a reference node, a resistor coupled between the RC circuit output terminal and a power supply node, and a capacitor coupled between the RC circuit output terminal and one of the power supply node or the reference node, and the inverter and the RC circuit are configured to generate an output signal at the output terminal based on the input signal.Type: GrantFiled: December 9, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wan-Yen Lin, Yuan-Ju Chan, Bo-Ting Chen
-
Publication number: 20230371696Abstract: A seat apparatus having a simulated force feedback and a method for simulating a force sensation of driving are provided. The seat apparatus includes a seating unit, a rotary platform, and a realistic seat pallet. The seating unit includes a seat pan. The rotary platform includes a chassis and a rotary motive module. The seat pan is disposed on the chassis along a rotation axis in an inclinable manner. The rotary motive module can control the seat pan to have a forward or rearward inclined angle. The realistic seat pallet is disposed on the seat pan, and includes a movable contact cushion and a pallet motive module. Through the pallet motive module, the movable contact cushion is slidable relative to the seat pan. The pallet motive module can control the movable contact cushion to have left and right displacements, front and rear displacements, angular displacements, or yaw rotations.Type: ApplicationFiled: May 9, 2023Publication date: November 23, 2023Inventors: SHIANG-FONG CHEN, Bo-Ting Lin, CHI PAN, TZU-YUAN YU
-
Publication number: 20230064159Abstract: A method for identifying a wafer is provided, which includes the following steps. A marked frame is obtained from a wafer inspection picture. A gray scale index corresponding to the marked frame is calculated based on a gray scale value corresponding to each of multiple pixels included in the marked frame. The gray scale index indicates a proportion of pixels whose gray scale values are greater than a specified value. Whether a trace pattern in the marked frame is a scratch or a grain boundary is determined based on the gray scale index.Type: ApplicationFiled: August 3, 2022Publication date: March 2, 2023Applicant: GlobalWafers Co., Ltd.Inventors: Shang-Chi Wang, Chia-Jung Lee, Bo-Ting Lin, Chia-Chi Tsai
-
Publication number: 20220384582Abstract: Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Miin-Jang Chen, Tzong-Lin Jay Shieh, Bo-Ting Lin
-
Patent number: 11502176Abstract: Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.Type: GrantFiled: November 3, 2020Date of Patent: November 15, 2022Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Miin-Jang Chen, Tzong-Lin Jay Shieh, Bo-Ting Lin
-
Publication number: 20210074817Abstract: Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.Type: ApplicationFiled: November 3, 2020Publication date: March 11, 2021Inventors: Miin-Jang Chen, Tzong-Lin Jay Shieh, Bo-Ting Lin
-
Patent number: 10847623Abstract: Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.Type: GrantFiled: December 28, 2018Date of Patent: November 24, 2020Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Miin-Jang Chen, Tzong-Lin Jay Shieh, Bo-Ting Lin
-
Publication number: 20200098871Abstract: Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.Type: ApplicationFiled: December 28, 2018Publication date: March 26, 2020Inventors: Miin-Jang Chen, Tzong-Lin Jay Shieh, Bo-Ting Lin
-
Publication number: 20190207035Abstract: A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate stack includes a dielectric material layer, a ferroelectric ZrO2 layer and a first conductive layer. The NCFET also includes a source/drain feature disposed in the substrate adjacent the gate stack.Type: ApplicationFiled: March 14, 2019Publication date: July 4, 2019Inventors: Miin-Jang Chen, Chi-Wen Liu, Bo-Ting Lin
-
Publication number: 20170365719Abstract: A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate stack includes a dielectric material layer, a ferroelectric ZrO2 layer and a first conductive layer. The NCFET also includes a source/drain feature disposed in the substrate adjacent the gate stack.Type: ApplicationFiled: June 15, 2016Publication date: December 21, 2017Inventors: Miin-Jang Chen, Chi-Wen Liu, Bo-Ting Lin
-
Publication number: 20090238069Abstract: A device for controlling program stream flow is described. The device is capable of saving power during computation. The device may include a de-multiplex unit and a direct memory access controller. The de-multiplex unit, for de-multiplexing a plurality of data, may include a request module for generating a request signal. The direct memory access controller is for receiving the request signal. The direct memory access controller obtains a plurality of data from a bus and sends the plurality of data to the de-multiplex unit according to the request signal.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Bo-Ting Lin, Shih-Ta Hsu
-
Publication number: 20090225768Abstract: A de-multiplexer is disclosed. A transport stream de-multiplexer includes a plurality of input buffers (211-21N) each receiving bytes from a plurality of packets in a corresponding transport stream, a main buffer (230) for temporal storage of said packets and an input arbiter temporally allotting a space of at least one packet in the main buffer to one of said packets when receiving a request to store a first byte of said packets into said main buffer.Type: ApplicationFiled: March 6, 2008Publication date: September 10, 2009Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Shih-Ta Hsu, Bo-Ting Lin
-
Publication number: 20030202665Abstract: An implementation method of 3D audio, which uses Head-Related Transfer Function (HRTF) to synthesize binaural sound from a monaural source. The implementation method of 3D audio includes the step of establishing a monaural Head-Related Transform Function (HRTF) database and an Interaural Time Delay (ITD) compensation curve by operating a monaural HRTF measurement, which records a set of HRTF coefficients for one ear, so that an externally input monaural signal is converted into a 3D sound signal according to the monaural HRTF database and the ITD compensation curve.Type: ApplicationFiled: April 24, 2002Publication date: October 30, 2003Inventors: Bo-Ting Lin, Chi-Fon Wu