Patents by Inventor Bo-un Yoon

Bo-un Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10428242
    Abstract: A slurry composition for chemical mechanical polishing, the slurry composition including ceramic polishing particles; a dispersion agent; a pH control agent and an additive having affinity with silicon nitride.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: October 1, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., K.C. TECH Co., Ltd.
    Inventors: Doo-sik Moon, Sang-hyun Park, Bo-un Yoon, Ho-young Kim, Se-jung Park, Jae-hak Lee, Jin-myung Hwang
  • Patent number: 10424503
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Patent number: 10403640
    Abstract: A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang Sun Hwang, Ki Chul Park, Young Beom Pyon, Byoung Ho Kwon, Bo Un Yoon
  • Patent number: 10297474
    Abstract: A chemical supplier includes a chemical reservoir containing a chemical mixture at a room temperature, an inner space of the chemical reservoir being separated from surroundings, a supply line through which the chemical mixture is supplied to a process chamber from the chemical reservoir, an inline heater positioned on the supply line and heating the chemical mixture in the supply line to a process temperature, and a power source driving the chemical mixture to move the chemical mixture toward the process chamber.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Jeong-Nam Han, Kee-Sang Kwon, Doo-Sung Yun, Won-Sang Choi
  • Publication number: 20190074289
    Abstract: A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.
    Type: Application
    Filed: March 22, 2018
    Publication date: March 7, 2019
    Inventors: Chang Sun Hwang, Ki Chul Park, Young Beom Pyon, Byoung Ho Kwon, Bo Un Yoon
  • Publication number: 20190043860
    Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.
    Type: Application
    Filed: October 12, 2018
    Publication date: February 7, 2019
    Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
  • Patent number: 10192973
    Abstract: A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Ha-Young Jeon, Byung-Kwon Cho, Jeong-Nam Han
  • Publication number: 20180374859
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Application
    Filed: August 29, 2018
    Publication date: December 27, 2018
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Patent number: 10128246
    Abstract: Semiconductor devices are provided. A semiconductor device includes a fin protruding from a substrate. Moreover, the semiconductor device includes first and second gate structures on the fin, and an isolation region between the first and second gate structures. The isolation region includes first and second portions having different respective widths. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Ha-Young Jeon, Yeon-Jin Gil, Ji-Won Yun, Won-Sang Choi
  • Patent number: 10128236
    Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
  • Patent number: 10109529
    Abstract: A semiconductor device including a direct contact and a bit line in a cell array region and a gate electrode structure in a peripheral circuit region, and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate including a cell array region including a first active region and a peripheral circuit region including a second active region, a first insulating layer on the substrate, the first insulating layer including contact holes exposing the first active region, a direct contact in the contact holes, wherein a direct contact is connected to the first active region, a bit line connected to the direct contact in the cell array region and extending in a first direction, and a gate insulating layer and a gate electrode structure, wherein a dummy conductive layer including substantially the same material as the direct contact is in the peripheral circuit region.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: October 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-ho Koh, Byoung-ho Kwon, Yang-hee Lee, Young-kuk Kim, In-seak Hwang, Bo-un Yoon
  • Patent number: 10096605
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Publication number: 20180282581
    Abstract: A slurry composition for chemical mechanical polishing, the slurry composition including ceramic polishing particles; a dispersion agent; a pH control agent and an additive having affinity with silicon nitride.
    Type: Application
    Filed: February 15, 2018
    Publication date: October 4, 2018
    Applicant: K.C. TECH Co., Ltd.
    Inventors: Doo-sik MOON, Sang-hyun PARK, Bo-un YOON, Ho-young KIM, Se-jung PARK, Jae-hak LEE, Jin-myung HWANG
  • Patent number: 10090190
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sang Youn, Myung-Geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Patent number: 10062786
    Abstract: A semiconductor device includes a first fin-type pattern on a substrate, having a first sidewall and a second sidewall opposed to each other; a first trench formed in contact with the first sidewall; a second trench formed in contact with the second sidewall; a first field insulating layer partially filling the first trench; and a second field insulating layer partially filling the second trench and a second field insulating layer partially filling the second trench. The second field insulating layer includes a first region and a second region disposed in a sequential order starting from the second sidewall, an upper surface of the second region being higher than an upper surface of the first field insulating layer. The device further includes a gate electrode on the first fin-type pattern, the first field insulating layer and the second field insulating layer, the gate electrode intersecting the first fin-type pattern and overlapping the second region.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Hyun Kim, Ho-Young Kim, Se-Jung Park, Bo-Un Yoon
  • Patent number: 10056466
    Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: August 21, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Jae Lee, Ja-Eung Koo, Ho-Young Kim, Yeong-Bong Park, Il-Su Park, Bo-Un Yoon, Il-Young Yoon, Youn-Su Ha
  • Patent number: 10032890
    Abstract: Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: July 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Hwan Yim, Yeon-Tack Ryu, Joo-Cheol Han, Ja-Eung Koo, No-Ul Kim, Ho-Young Kim, Bo-Un Yoon
  • Publication number: 20180197861
    Abstract: A first conductivity type finFET device can include first embedded sources/drains of a first material that have a first etch rate. The first embedded sources/drains can each include an upper surface having a recessed portion and an outer raised portion relative to the recessed portion. A second conductivity type finFET device can include second embedded sources/drains of a second material that have a second etch rate than is greater that the first etch rate. The second embedded sources/drains can each include an upper surface that is at a different level than the outer raised portions of the first conductivity type finFET device.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Inventors: Sang Jine Park, KI HYUNG KO, KEE SANG KWON, JAE JIK BAEK, BO UN YOON, YONG SUN KO
  • Publication number: 20180174889
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Application
    Filed: January 31, 2018
    Publication date: June 21, 2018
    Inventors: Young-Sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Publication number: 20180130672
    Abstract: A method of manufacturing a semiconductor device includes preparing an object layer on a substrate; polishing the object layer with a first slurry including a first abrasive having a zeta potential of a first polarity; rinsing a surface of the object layer, using a rinsing solution including a chemical of a second polarity, opposite to the first polarity; and polishing the object layer with a second slurry including a second abrasive having a zeta potential of a second polarity, opposite to the first polarity.
    Type: Application
    Filed: October 2, 2017
    Publication date: May 10, 2018
    Applicant: Samsung Electronics Co., Ltd .
    Inventors: Hyo Jung Kim, Ye Hwan Kim, Ki Hoon Jang, Byoung Ho Kwon, Bo Un Yoon