Patents by Inventor Bo-un Yoon

Bo-un Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240063044
    Abstract: A method of fabricating a semiconductor device comprises mounting a carrier substrate and a wafer on a wafer chuck of a wafer chuck apparatus, the carrier substrate and the wafer attached to each other, injecting air into an air member by selectively controlling at least one air injection pipe connected to the air member of the wafer chuck apparatus, tilting the wafer chuck to a predetermined angle in response to the air being injected into the air member, processing the wafer while the wafer chuck is tilted, determining whether to change a tilt angle of the wafer chuck or a position of the wafer, adjusting an amount of air injected into the air member according to a changed tilt angle of the wafer chuck or a changed position of the wafer, and processing the wafer after adjusting of the amount of air in the air member.
    Type: Application
    Filed: May 27, 2023
    Publication date: February 22, 2024
    Inventors: Dong Hoon KWON, Ju Hyun LEE, Bo Un YOON
  • Patent number: 11791173
    Abstract: Substrate cleaning equipment includes a substrate holder which supports a substrate, a swing body, a head, a first cleaning liquid supply structure, and a second cleaning liquid supply structure. The swing body moves along a sweep line on a main surface of the substrate. The head is coupled to the swing body and includes a pad attachment surface facing the substrate holder. The first cleaning liquid supply structure is coupled to the swing body and sprays a first cleaning liquid onto the main surface of the substrate. The second cleaning liquid supply structure sprays a second cleaning liquid onto the main surface of the substrate. A buffing pad is attached to the pad attachment surface.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Hoon Choi, Ja Eung Koo, No Ui Kim, Hyun Kyo Seo, Tae Min Earmme, Bo Un Yoon, Youn Cheol Jeong
  • Publication number: 20230211456
    Abstract: A polishing pad for chemical mechanical polishing includes a polymer matrix and a temperature sensitive agent dispersed in the polymer matrix and constituting 1 to 40% by volume of the polishing pad, wherein the temperature sensitive agent includes a two-dimensional (2D) sheet material having a thermal conductivity of 1 W/(m·K) or more.
    Type: Application
    Filed: December 15, 2022
    Publication date: July 6, 2023
    Inventors: Yea Rin Byun, In Kwon Kim, Bo Yun Kim, Sang Kyun Kim, Bo Un Yoon, Hyo San Lee, Byung Keun Hwang
  • Publication number: 20230170222
    Abstract: A method for fabricating a semiconductor device includes providing a polishing pad which includes a first region and a second region separated from each other by a fence, loading a wafer onto the first region, providing a slurry solution onto the first region, providing an ultrapure water onto the second region, turning the polishing pad to polish a surface of the wafer, and unloading the wafer from the polishing pad after polishing on the surface of the wafer is completed, wherein the fence includes a first fence extending from a center of the polishing pad toward an edge of the polishing pad in a first horizontal direction, and a second fence extending from the center of the polishing pad toward the edge of the polishing pad in a second horizontal direction different from the first horizontal direction.
    Type: Application
    Filed: June 17, 2022
    Publication date: June 1, 2023
    Inventors: Dong Hoon KWON, Chung Ki MIN, Bo Un YOON, Ki Hoon JANG
  • Patent number: 11581318
    Abstract: A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: February 14, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye Sung Park, Jong Hyuk Park, Jin Woo Bae, Bo Un Yoon, Il Young Yoon, Bong Sik Choi
  • Publication number: 20210242215
    Abstract: A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.
    Type: Application
    Filed: April 22, 2021
    Publication date: August 5, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hye Sung PARK, Jong Hyuk PARK, Jin Woo BAE, Bo Un YOON, Il Young YOON, Bong Sik CHOI
  • Patent number: 11011526
    Abstract: A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: May 18, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye Sung Park, Jong Hyuk Park, Jin Woo Bae, Bo Un Yoon, Il Young Yoon, Bong Sik Choi
  • Patent number: 10964751
    Abstract: A semiconductor device that includes a plurality of word lines disposed on a substrate in which p-type and n-type active regions are defined, and extends in a first direction. A plurality of bit lines is disposed on the plurality of word lines and extends in a second direction, perpendicular to the first direction. A plurality of memory cells is disposed between the plurality of word lines and the plurality of bit lines and each includes a data storage pattern. The plurality of memory cells includes a plurality of dummy memory cells and a plurality of main memory cells. An upper surface of the data storage pattern of the main memory cells is higher than an upper surface of the data storage pattern of the dummy memory cells.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hao Cui, Se Yun Park, Jong Hyuk Park, Bo Un Yoon, Il Young Yoon
  • Patent number: 10943908
    Abstract: A method of forming a semiconductor device includes forming a mold structure on a substrate, forming a first mask layer having a deposition thickness on the mold structure and patterning the first mask layer to form first mask openings which expose the mold structure. The mold structure is etched to form holes that penetrate the mold structure. The first mask layer is thinned to form mask portions having thickness smaller than the deposition thickness. Conductive patterns are formed to fill the holes and the first mask openings. The first mask layer including the mask portions is etched to expose the mold structure. The conductive patterns include protrusions. A chemical mechanical polishing process is performed to remove the protrusions of the conductive patterns.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin Woo Bae, Su Young Shin, Young Ho Koh, Bo Un Yoon, Il Young Yoon, Yang Hee Lee, Hee Sook Cheon
  • Patent number: 10829690
    Abstract: Disclosed is a slurry composition for chemical mechanical polishing (CMP) includes, as polishing particles, a complex compound of both fullerenol and alkylammonium hydroxide. The slurry composition, which exhibits excellent polishing properties, may be prepared at low cost in large quantities. Also disclosed is a method of preparing the slurry composition comprising obtaining a mixture of a fullerenol complex compound and unreacted hydrogen peroxide by reacting alkylammonium hydroxide, hydrogen peroxide, and fullerene, removing the unreacted hydrogen peroxide by adding hydrogen peroxide decomposition catalyst particles to the mixture, separating the hydrogen peroxide decomposition catalyst particles from the mixture by filtration, and adding a polishing additive to the mixture.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bo-yun Kim, Kenji Takai, Do-yoon Kim, Sang-kyun Kim, Bo-un Yoon
  • Publication number: 20200303218
    Abstract: Substrate cleaning equipment includes a substrate holder which supports a substrate, a swing body, a head, a first cleaning liquid supply structure, and a second cleaning liquid supply structure. The swing body moves along a sweep line on a main surface of the substrate. The head is coupled to the swing body and includes a pad attachment surface facing the substrate holder. The first cleaning liquid supply structure is coupled to the swing body and sprays a first cleaning liquid onto the main surface of the substrate. The second cleaning liquid supply structure sprays a second cleaning liquid onto the main surface of the substrate. A buffing pad is attached to the pad attachment surface.
    Type: Application
    Filed: January 13, 2020
    Publication date: September 24, 2020
    Inventors: SEUNG HOON CHOI, JA EUNG KOO, NO UI KIM, HYUN KYO SEO, TAE MIN EARMME, BO UN YOON, YOUN CHEOL JEONG
  • Patent number: 10741409
    Abstract: A method of manufacturing a semiconductor device includes preparing an object layer on a substrate; polishing the object layer with a first slurry including a first abrasive having a zeta potential of a first polarity; rinsing a surface of the object layer, using a rinsing solution including a chemical of a second polarity, opposite to the first polarity; and polishing the object layer with a second slurry including a second abrasive having a zeta potential of a second polarity, opposite to the first polarity.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo Jung Kim, Ye Hwan Kim, Ki Hoon Jang, Byoung Ho Kwon, Bo Un Yoon
  • Patent number: 10734380
    Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
  • Publication number: 20200235165
    Abstract: A semiconductor device that includes a plurality of word lines disposed on a substrate in which p-type and n-type active regions are defined, and extends in a first direction. A plurality of bit lines is disposed on the plurality of word lines and extends in a second direction, perpendicular to the first direction. A plurality of memory cells is disposed between the plurality of word lines and the plurality of bit lines and each includes a data storage pattern. The plurality of memory cells includes a plurality of dummy memory cells and a plurality of main memory cells. An upper surface of the data storage pattern of the main memory cells is higher than an upper surface of the data storage pattern of the dummy memory cells.
    Type: Application
    Filed: September 27, 2019
    Publication date: July 23, 2020
    Inventors: Hao CUI, Se Yun PARK, Jong Hyuk PARK, Bo Un YOON, II Young YOON
  • Publication number: 20200227315
    Abstract: A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.
    Type: Application
    Filed: September 9, 2019
    Publication date: July 16, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hye Sung PARK, Jong Hyuk PARK, Jin Woo BAE, Bo Un YOON, II Young YOON, Bong Sik CHOI
  • Publication number: 20200098763
    Abstract: A method of forming a semiconductor device includes forming a mold structure on a substrate, forming a first mask layer having a deposition thickness on the mold structure and patterning the first mask layer to form first mask openings which expose the mold structure. The mold structure is etched to form holes that penetrate the mold structure. The first mask layer is thinned to form mask portions having thickness smaller than the deposition thickness. Conductive patterns are formed to fill the holes and the first mask openings. The first mask layer including the mask portions is etched to expose the mold structure. The conductive patterns include protrusions. A chemical mechanical polishing process is performed to remove the protrusions of the conductive patterns.
    Type: Application
    Filed: May 14, 2019
    Publication date: March 26, 2020
    Inventors: JIN WOO BAE, Su Young SHIN, Young Ho KOH, Bo Un YOON, II Young YOON, Yang Hee LEE, Hee Sook CHEON
  • Publication number: 20200071613
    Abstract: Disclosed is a slurry composition for chemical mechanical polishing (CMP) includes, as polishing particles, a complex compound of both fullerenol and alkylammonium hydroxide. The slurry composition, which exhibits excellent polishing properties, may be prepared at low cost in large quantities. Also disclosed is a method of preparing the slurry composition comprising obtaining a mixture of a fullerenol complex compound and unreacted hydrogen peroxide by reacting alkylammonium hydroxide, hydrogen peroxide, and fullerene, removing the unreacted hydrogen peroxide by adding hydrogen peroxide decomposition catalyst particles to the mixture, separating the hydrogen peroxide decomposition catalyst particles from the mixture by filtration, and adding a polishing additive to the mixture.
    Type: Application
    Filed: July 3, 2019
    Publication date: March 5, 2020
    Inventors: Bo-yun KIM, Kenji Takai, Do-yoon KIM, Sang-kyun KIM, Bo-un YOON
  • Publication number: 20190341358
    Abstract: A method of forming a semiconductor device, includes: forming a design pattern on a substrate, wherein the design pattern protrudes from the substrate; forming a filling layer on the substrate, wherein the filling layer at least partially covers the design pattern; forming a polishing resistance pattern adjacent to the design pattern in the filling layer using a laser irradiation process and/or an ion implantation process; and removing the filling layer using a chemical mechanical polishing (CMP) process to expose the design pattern.
    Type: Application
    Filed: January 21, 2019
    Publication date: November 7, 2019
    Inventors: YANG HEE LEE, Jong Hyuk Park, Jin Woo Bae, Choong Seob Shin, Hyo Jin Oh, Bo Un Yoon, Il Young Yoon, Hee Sook Cheon
  • Patent number: 10446561
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: October 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Patent number: 10428242
    Abstract: A slurry composition for chemical mechanical polishing, the slurry composition including ceramic polishing particles; a dispersion agent; a pH control agent and an additive having affinity with silicon nitride.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: October 1, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., K.C. TECH Co., Ltd.
    Inventors: Doo-sik Moon, Sang-hyun Park, Bo-un Yoon, Ho-young Kim, Se-jung Park, Jae-hak Lee, Jin-myung Hwang