Abstract: A comparison apparatus and a speed-up method for comparator are provided. The comparison apparatus consists of a comparator and a bias modulator. The bias modulator receives input signals of the comparator to provide a set of output signals modulated according to the input signals. The set of output signals dynamically adjust body voltages of transistors in a positive feedback network of the comparator to increase a switching speed of the transistors. Therefore, an operation speed of the comparator can also be increased.

Abstract: A switched-capacitor (SC) circuit relating to summing and integration algorithms is provided. The SC circuit submitted by the present invention benefits from better closed-loop bandwidth performance because of combining positive and negative feedback loops of a high gain amplifier. In addition, the SC circuit submitted by the present invention not only provides differential output signal obtained by a summing (or integration) algorithm of input voltage signals and reference voltage signals and forward drives such differential output signal to a next stage SC circuit, but also provides flexible and accurate coefficient design for every individual input and reference voltage signals in the said algorithm. Besides, if the circuit manner of alternate resetting is disabled or removed, the SC summing circuit submitted by the present invention can serve as an SC integration circuit.

Abstract: A video summarized method based on mining the story structure and semantic relations among concept entities has steps of processing a video to generate multiple important shots that are annotated with respective keywords: Performing a concept expansion process by using the keywords to create expansion trees for the annotated shots; rearranging the keywords of the expansion trees and classifying to calculate relations thereof; applying a graph entropy algorithm to determine significant shots and edges interconnected with the shots. Based on the determined result of the graph entropy algorithm, a structured relational graph is built to display the significant shots and edges thereof. Consequently, users can more rapidly browse the content of a video and comprehend if different shots are related.

Abstract: A dynamic comparator with background offset calibration is provided. The dynamic comparator includes at least one input differential pair, a first back-to-back inverter, a second back-to-back inverter, and an integrator. The input differential pair includes two current branches, wherein one of the current branches has an input referred offset. The first back-to-back inverter determines which one of the two current branches has the input referred offset in response to a first clock signal and generates two control signals accordingly. The integrator generates two calibration voltages for the input differential pair in response to the two control signals, so as to calibrate the input referred offset. The second back-to-back inverter determines a difference between two input signals received by the input differential pair after the input referred offset is calibrated in response to a second clock signal and outputs two comparison signals accordingly.

Abstract: An automatic scan and mark apparatus has a machine tool, a location detection module, a laser detector, an ink jet and a control computer. The machine tool has a movable module and a stage. The stage mounts and holds a specimen having a scraped surface. The control computer controls the location detection module to determine a position of the movable module, controls the laser detector to detect a surface morphology of the scraped surface in a measurement range, and activates the ink jet to eject inks on high points of the scraped surface of the specimen. Thus, the surface morphology is built automatically and high points are screened out and marked by colored ink. Manufacturer may easily redo scraping of determined high points based on the marked location on the specimen without burdensome measurement.

Abstract: The present invention relates to a method to fabricate a flip chip substrate structure, which comprises: providing a carrier; forming a patterned resist layer on the surface of the carrier; forming sequentially a first metal layer, an etching-stop layer, and a second metal layer; removing the resist layer, forming a patterned first solder mask, and then forming at least one first circuit build up structure thereon; forming additionally a patterned second solder mask on the circuit build up structure; respectively removing the carrier, the first metal layer, and the etching-stop layer; and forming solder bumps on both sides of the circuit build up structure. The method increases integration and achieves the purpose of miniaturization. The method solves the problem of circuit layer multiplicity and process complexity.

Abstract: A bandgap reference circuit generating bandgap reference voltage/current. The bandgap reference circuit generates a negative temperature coefficient current (ICTAT) and the first and the second positive temperature coefficient currents (IPTAT and INL), and compensates the non-constant components of the current ICTAT by multiplying the currents ICTAT, IPTAT and INL by three specially designed numbers K1, K2 and K3, respectively, and then summing up the results. The bandgap reference circuit transforms the summation current (K1·ICTAT+K2·IPTAT+K3·INL) to generate a bandgap reference voltage or a bandgap reference current.

Abstract: A method of manufacturing a coreless package substrate together with a conductive structure of the substrate is disclosed. The method can produce a coreless package substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless package substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A bandgap reference circuit generating bandgap reference voltage/current. The bandgap reference circuit generates a negative temperature coefficient current (ICTAT) and the first and the second positive temperature coefficient currents (IPTAT and INL), and compensates the non-constant components of the current ICTAT by multiplying the currents ICTAT, IPTAT and INL by three specially designed numbers K1, K2 and K3, respectively, and then summing up the results. The bandgap reference circuit transforms the summation current (K1·ICTAT+K2·IPTAT+K3·INL) to generate a bandgap reference voltage or a bandgap reference current.

Abstract: A novel analog-to-digital converter (ADC) architecture using subranging successive approximation approach is disclosed. The ADC architecture is capable of achieving high sampling rate, low power consumption and low complexity. It is also able to advance the chip production yield and area utilization ratio. The new proposed ADC is formed by combining a flash converter having high sampling rate and low resolution with a successive approximation converter having low power consumption and low sampling rate.

Abstract: A method for manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A method of manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A novel analog-to-digital converter (ADC) architecture using subranging successive approximation approach is disclosed. The ADC architecture is capable of achieving high sampling rate, low power consumption and low complexity. It is also able to advance the chip production yield and area utilization ratio. The new proposed ADC is formed by combining a flash converter having high sampling rate and low resolution with a successive approximation converter having low power consumption and low sampling rate.

Abstract: The package substrate of the present invention comprises a carrying board, bump pads, wire bonding pads, a solder mask, metallic bumps, and a metallic protective layer. The solder pads and the wire bonding pads are disposed on the surface of the carrying board. The solder mask is patterned to expose bump pads, wire bonding pads, and part of the surface of the substrate on the periphery of the wire bonding pads. The metallic bumps are disposed on the surface of the bump pads and extend to the surface of the solder mask. The metallic protective layer is disposed on the surfaces of the metallic bumps and the wire bonding pads. Besides, a method for manufacturing this package substrate, a semiconductor package structure comprising this package substrate, and a manufacturing method thereof are disclosed. Therefore, the manufacturing process of the package substrate is simple, and the package substrate is slim.

Abstract: The present invention relates to a method to fabricate a flip chip substrate structure, which comprises: providing a carrier; forming a patterned resist layer on the surface of the carrier; forming sequentially a first metal layer, an etching-stop layer, and a second metal layer; removing the resist layer, forming a patterned first solder mask, and then forming at least one first circuit build up structure thereon; forming additionally a patterned second solder mask on the circuit build up structure; respectively removing the carrier, the first metal layer, and the etching-stop layer; and forming solder bumps on both sides of the circuit build up structure. The method increases integration and achieves the purpose of miniaturization. The method solves the problem of circuit layer multiplicity and process complexity.

Abstract: A flip chip substrate structure and a method to fabricate thereof are disclosed. The structure comprises a build up structure, a first solder mask and a second solder mask. Plural first and second electrical contact pads are formed on the first and second surface of the build up structure, respectively. A first solder mask having plural openings is formed on the first surface of the build up structure, and the openings expose the first electrical contact pads, wherein the aperture of the openings of the first solder mask are equal to the outer diameter of the first electrical contact pads. A second solder mask having plural openings is formed on the second surface of the build up structure, and the openings expose the second electrical contact pads, wherein the aperture of the openings of the second solder mask are smaller than the outer diameter of the second electrical contact pads.

Abstract: A method for manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A method of manufacturing a coreless package substrate together with a conductive structure of the substrate is disclosed. The method can produce a coreless package substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless package substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A method of manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A novel analog-to-digital converter (ADC) architecture using subranging successive approximation approach is disclosed. The ADC architecture is capable of achieving high sampling rate, low power consumption and low complexity. It is also able to advance the chip production yield and area utilization ratio. The new proposed ADC is formed by combining a flash converter having high sampling rate and low resolution with a successive approximation converter having low power consumption and low sampling rate.