Patents by Inventor Bo-Wei Hsieh

Bo-Wei Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210295894
    Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.
    Type: Application
    Filed: April 22, 2021
    Publication date: September 23, 2021
    Applicant: MediaTek Inc.
    Inventors: Bo-Wei Hsieh, Ching-Yeh Hsuan, Shang-Pin Chen
  • Patent number: 11127780
    Abstract: A display panel including data lines, scan lines, pixel structures, power lines and a fixing layer is provided. The pixel structure includes a first transistor, a second transistor and a light emitting diode device. The first transistor is electrically coupled to a corresponding scan line, a corresponding data line and the second transistor. A first end of the light emitting diode device is electrically coupled to the second transistor. The power lines are electrically coupled to the second transistor of at least one of the pixel structures and a second end of the light emitting diode device of at least one of the pixel structures. The fixing layer is disposed on at least one of the power lines. The light emitting diode device of at least one of the pixel structures is disposed on the fixing layer and overlapped with the at least one of the power lines.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: September 21, 2021
    Assignee: Au Optronics Corporation
    Inventors: Bo-Shiang Tzeng, Chia-Wei Kuo, Chia-Ting Hsieh, Pin-Miao Liu
  • Publication number: 20210174851
    Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.
    Type: Application
    Filed: February 19, 2021
    Publication date: June 10, 2021
    Applicant: Media Tek Inc.
    Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Jou-Ling Chen
  • Patent number: 11017839
    Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: May 25, 2021
    Assignee: MediaTek Inc.
    Inventors: Bo-Wei Hsieh, Ching-Yeh Hsuan, Shang-Pin Chen
  • Patent number: 10964363
    Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 30, 2021
    Assignee: MediaTek Inc.
    Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Jou-Ling Chen
  • Patent number: 10878879
    Abstract: A refresh control method for a memory controller of a memory system is provided. The memory controller is connected with a memory. The memory includes plural memory banks. The refresh control method includes the following steps. Firstly, a refresh state of the memory device is read, and thus a refresh window is realized. Then, a refresh command is issued to the memory device according to the refresh state. The refresh command contains a memory bank number field and a memory bank count field. The memory bank count field indicates a first count. The first count of memory banks are selected from the plural memory banks of the memory device according to the memory bank number field and the first count. Moreover, a refresh operation is performed on the first count of memory banks.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 29, 2020
    Assignee: MediaTek Inc.
    Inventors: Der-Ping Liu, Bo-Wei Hsieh
  • Patent number: 10846018
    Abstract: A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: November 24, 2020
    Assignee: MEDIATEK INC.
    Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Shang-Pin Chen
  • Patent number: 10810078
    Abstract: A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: October 20, 2020
    Assignee: MEDIATEK INC.
    Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Ching-Yeh Hsuan, Jou-Ling Chen
  • Publication number: 20200058335
    Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 20, 2020
    Inventors: Bo-Wei HSIEH, Chia-Yu CHAN, Jou-Ling CHEN
  • Publication number: 20200012558
    Abstract: A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.
    Type: Application
    Filed: July 2, 2019
    Publication date: January 9, 2020
    Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Ching-Yeh Hsuan, Jou-Ling Chen
  • Publication number: 20190074051
    Abstract: A refresh control method for a memory system is provided. The memory system includes a dynamic random access memory with a register set and a memory cell array. The refresh control method includes the following steps. Firstly, a masking command or an unmasking command is issued, and thus the register set is updated. A first region of the memory cell array is set as a masked region according to the masking command. A second region of the memory cell array is set as an unmasked region according to the unmasking command. Then, a refresh command is issued to the dynamic random access memory. According to the refresh command, a refresh action is performed on the second region of the memory cell array.
    Type: Application
    Filed: June 1, 2018
    Publication date: March 7, 2019
    Inventors: Chia-Fu CHANG, Hsiang-I HUANG, Bo-Wei HSIEH, Szu-Ying CHENG, Yu-Hsien TSAI
  • Publication number: 20180374533
    Abstract: A refresh control method for a memory controller of a memory system is provided. The memory controller is connected with a memory. The memory includes plural memory banks. The refresh control method includes the following steps. Firstly, a refresh state of the memory device is read, and thus a refresh window is realized. Then, a refresh command is issued to the memory device according to the refresh state. The refresh command contains a memory bank number field and a memory bank count field. The memory bank count field indicates a first count. The first count of memory banks are selected from the plural memory banks of the memory device according to the memory bank number field and the first count. Moreover, a refresh operation is performed on the first count of memory banks.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 27, 2018
    Inventors: Der-Ping Liu, Bo-Wei Hsieh
  • Patent number: 10163485
    Abstract: A memory module includes a memory interface circuit and a training signal generator. The memory interface circuit includes a plurality of terminals for communicating with a memory controller, and the terminals comprise at least a plurality of data terminals. The training signal generator is coupled to the memory interface circuit, and is arranged for generating a training signal to the memory controller through only a portion of the data terminals or a specific terminal instead of the data terminals when the memory module receives a training request from the memory controller.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: December 25, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Bo-Wei Hsieh
  • Patent number: 10141044
    Abstract: A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: November 27, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
  • Patent number: 10109341
    Abstract: A memory controller is connected with a memory. The memory controller includes a clock signal pin and plural command pins. The clock signal pin is connected with the memory for transmitting a clock signal to the memory. The plural command pins are connected with the memory for transmitting a command signal to the memory. The command signal contains an entering self-refresh command and an entering power down command. The memory enters a self-refresh state when the entering self-refresh command is executed. The memory enters a power down state when the entering power down command is executed.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: October 23, 2018
    Assignee: MEDIATEK INC.
    Inventors: Bo-Wei Hsieh, Shang-Pin Chen
  • Publication number: 20180293026
    Abstract: A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.
    Type: Application
    Filed: March 26, 2018
    Publication date: October 11, 2018
    Inventors: Bo-Wei HSIEH, Chia-Yu CHAN, Shang-Pin CHEN
  • Patent number: 10083728
    Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive a second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.
    Type: Grant
    Filed: July 6, 2014
    Date of Patent: September 25, 2018
    Assignee: MediaTek Inc.
    Inventors: Yan-Bin Luo, Sheng-Ming Chang, Bo-Wei Hsieh, Ming-Shi Liou, Chih-Chien Hung, Shang-Pin Chen
  • Publication number: 20180204610
    Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.
    Type: Application
    Filed: January 5, 2018
    Publication date: July 19, 2018
    Inventors: Bo-Wei HSIEH, Ching-Yeh HSUAN, Shang-Pin CHEN
  • Patent number: 10008255
    Abstract: An operating method for a dynamic random access memory (DRAM) obtains a plurality of first sub-commands of a first activate command via a command bus, and obtaining a plurality of first address information regarding a plurality of first portions of a first row address of a specific bank via an address bus. Each of the first sub-commands corresponds to an individual first portion of the first row address of the specific bank. The method further combines the first portions of the first row address of the specific bank in response to a specific sub-command of the first sub-commands, so as to obtain a first complete row address; and obtains an access command via the command bus.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: June 26, 2018
    Assignee: MEDIATEK INC.
    Inventor: Bo-Wei Hsieh
  • Patent number: 9871518
    Abstract: A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: January 16, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh