Abstract: A memory test apparatus includes a test board unit including a first test board configured to load for testing a first memory system including a plurality of memory modules. A second test board is configured to load for testing a second memory system including a plurality of memory modules. A power unit comprises a first power supply unit configured to supply the first test board with a first power for testing the first memory system, a second power supply unit configured to supply the second test board with a second power for testing the second memory system, and a power supply control unit configured to control at least one of a supply timing of the first power and a supply timing of the second power.