Abstract: The present invention provides a Ganoderma lucidum ?-glucan extract, a preparation method and detection method therefor. The preparation method includes: S1: crushing fruiting bodies of Ganoderma lucidum, mixing the crushed fruiting bodies with a solvent, adding trypsin for enzymatic hydrolysis for 0.5-2 h, and separating to obtain a Ganoderma lucidum fruiting body filter residue; S2: mixing the Ganoderma lucidum fruiting body filter residue with an alkali solution, carrying out ultrasonic extraction with heating, adjusting the pH value of the obtained filtrate to be neutral, and concentrating to obtain a crude Ganoderma lucidum polysaccharide; S3: carrying out alcohol precipitation on the crude Ganoderma lucidum polysaccharide, separating the obtained precipitate, and freeze-drying to obtain a crude Ganoderma lucidum ?-glucan extract; and S4: purifying the crude Ganoderma lucidum ?-glucan extract by glucose gel column chromatography to obtain a Ganoderma lucidum ?-glucan extract.

Abstract: A fingerprint spectrum construction method for a new compound aloe capsule and a fingerprint spectrum includes: (1) taking powder of a new compound aloe capsule, carrying out reflux extraction, adding methanol, carrying out ultrasonic treatment, filtering, and taking a subsequent filtrate as a test solution; dissolving barbaloin, aloe-emodin, indirubin, tryptanthrin, aloesin, and ?-sitosterol in methanol to obtain reference solutions; (2) injecting the test solution and the reference solutions into a high performance liquid chromatograph for gradient elution to obtain a chromatogram of the new compound aloe capsule and chromatograms of the reference solutions, respectively; and (3) labeling chemical components of peaks on the chromatogram of the new compound aloe capsule according to the chromatogram of the new compound aloe capsule and the chromatograms of the reference solutions to obtain a fingerprint spectrum of the new compound aloe capsule.

Abstract: A duty cycle correction circuit includes: a first inverter, a first delayer, and a first adjustment circuit. An input terminal and output terminal of the first inverter are respectively configured to receive a first signal and output a third signal. A first input terminal and an output terminal of the first adjustment circuit are respectively configured to receive the third signal and output a first correction signal. An input terminal and output terminal of the first delayer are respectively configured to input a second signal and output a fourth signal to the first adjustment circuit. The fourth signal has a first delay time relative to the second signal. When the third signal and the fourth signal are at a high level, so is the first correction signal. When the third signal and the fourth signal are at a low level, so is the first correction signal.

Abstract: A duty cycle correction circuit includes: a first inverter, a first delayer, and a first adjustment circuit. An input terminal and output terminal of the first inverter are respectively configured to receive a first signal and output a third signal. A first input terminal and an output terminal of the first adjustment circuit are respectively configured to receive the third signal and output a first correction signal. An input terminal and output terminal of the first delayer are respectively configured to input a second signal and output a fourth signal to the first adjustment circuit. The fourth signal has a first delay time relative to the second signal. When the third signal and the fourth signal are at a high level, so is the first correction signal. When the third signal and the fourth signal are at a low level, so is the first correction signal.

Abstract: A duty cycle correction circuit includes: a first inverter, a first delayer, and a first adjustment circuit. An input terminal and output terminal of the first inverter are respectively configured to receive a first signal and output a third signal. A first input terminal and an output terminal of the first adjustment circuit are respectively configured to receive the third signal and output a first correction signal. An input terminal and output terminal of the first delayer are respectively configured to input a second signal and output a fourth signal to the first adjustment circuit. The fourth signal has a delay of a first time duration relative to the second signal. When the third signal and the fourth signal are at a high level, so is the first correction signal. When the third signal and the fourth signal are at a low level, so is the first correction signal.

Abstract: A data interface is disclosed, which includes an electrostatic discharge circuit, and a charge transmitting circuit connected to a binding wire through the electrostatic discharge circuit; the charge transmitting circuit includes a first capacitor, the charge transmitting circuit transfers charges in the first capacitor to a parasitic capacitor of the electrostatic discharge circuit and a parasitic capacitor of the binding wire, to generate a first voltage signal and output the first voltage signal through the binding wire. According to the data interface, charges in a charging capacitor and a parasitic capacitor are redistributed, which could not only reduce a power consumption loss caused by a parasitic capacitor in a communication channel but also effectively reduce time delay. In addition, the use of dual-wire communication is avoided by using single-wire communication, and the manufacturing costs are reduced relative to low-voltage differential signaling (LVDS).

Abstract: A data interface is disclosed, which includes an electrostatic discharge circuit, and a charge transmitting circuit connected to a binding wire through the electrostatic discharge circuit; the charge transmitting circuit includes a first capacitor, the charge transmitting circuit transfers charges in the first capacitor to a parasitic capacitor of the electrostatic discharge circuit and a parasitic capacitor of the binding wire, to generate a first voltage signal and output the first voltage signal through the binding wire. According to the data interface, charges in a charging capacitor and a parasitic capacitor are redistributed, which could not only reduce a power consumption loss caused by a parasitic capacitor in a communication channel but also effectively reduce time delay. In addition, the use of dual-wire communication is avoided by using single-wire communication, and the manufacturing costs are reduced relative to low-voltage differential signaling (LVDS).