Abstract: A high-performance data storage device is disclosed. A non-volatile memory stores a logical-to-physical address mapping table that maps logical addresses recognized by a host to a physical space in the non-volatile memory. The logical-to-physical address mapping table is divided into a plurality of sub mapping tables. A memory controller utilizes temporary storage when controlling the non-volatile memory. The memory controller plans a sub mapping table area in the temporary storage to store sub mapping tables corresponding to a plurality of nodes which are linked and managed by multiple linked lists.

Abstract: A high-performance data storage device is disclosed, including a non-volatile memory, a controller, and a temporary storage. Sub mapping tables divided from a logical-to-physical address mapping table according to logical address groups are stored in mapping blocks allocated in the non-volatile memory. The controller limits the number of mapping blocks by garbage collection, and performs garbage collection on a source mapping block in sections. During each garbage collection section, the controller downloads valid sub mapping tables from the source mapping block to the temporary storage and then programs the valid sub mapping tables from the temporary storage to a destination mapping block. The temporary storage is repeatedly used to store valid sub mapping tables downloaded in the different garbage collection sections.

Abstract: A high-performance data storage device is disclosed. A non-volatile memory stores a logical-to-physical address mapping table that maps logical addresses recognized by a host to a physical space in the non-volatile memory. The logical-to-physical address mapping table is divided into a plurality of sub mapping tables. A memory controller utilizes temporary storage when controlling the non-volatile memory. The memory controller plans a sub mapping table area in the temporary storage to store sub mapping tables corresponding to a plurality of nodes which are linked and managed by multiple linked lists.

Abstract: A high-performance data storage device is disclosed, including a non-volatile memory, a controller, and a temporary storage. Sub mapping tables divided from a logical-to-physical address mapping table according to logical address groups are stored in mapping blocks allocated in the non-volatile memory. The controller limits the number of mapping blocks by garbage collection, and performs garbage collection on a source mapping block in sections. During each garbage collection section, the controller downloads valid sub mapping tables from the source mapping block to the temporary storage and then programs the valid sub mapping tables from the temporary storage to a destination mapping block. The temporary storage is repeatedly used to store valid sub mapping tables downloaded in the different garbage collection sections.