Abstract: A control circuit, comprising a storage circuit and a processor. The storage circuit is configured to store a retry sequence table and a plurality of read-voltage tables. The processor is coupled to the storage circuit, and is configured to access a memory comprising a plurality of blocks. When a read error occurs in a first block of the plurality of blocks, the processor sequentially uses the plurality of read-voltage tables to perform a retry test on the first block according to a retry sequence indicated by the retry sequence table. When a retry history data of the first block matches an adjustment condition, the processor adjusts the retry sequence indicated by the retry sequence table.

Abstract: A control circuit coupled to a memory through multiple channels. The plurality of channels comprises a first channel, and the control circuit comprises a storage circuit and a processor. The storage circuit is configured to store multiple read-voltage tables and an index register. The processor is coupled to the storage circuit. When an error occurs in a read operation of the first channel, the processor is configured to perform a first retry-read test to the memory through the first channel by sequentially using the multiple read-voltage tables until the first retry-read test is successfully performed by using a target read-voltage table of the multiple read-voltage tables. When the first retry-read test is successfully performed by the processor, the processor determines whether to update the index register according to an analysis of a change history of a stored data in the index register.

Abstract: A high-performance data storage device is disclosed. A non-volatile memory stores a logical-to-physical address mapping table that maps logical addresses recognized by a host to a physical space in the non-volatile memory. The logical-to-physical address mapping table is divided into a plurality of sub mapping tables. A memory controller utilizes temporary storage when controlling the non-volatile memory. The memory controller plans a sub mapping table area in the temporary storage to store sub mapping tables corresponding to a plurality of nodes which are linked and managed by multiple linked lists.

Abstract: A high-performance data storage device is disclosed, including a non-volatile memory, a controller, and a temporary storage. Sub mapping tables divided from a logical-to-physical address mapping table according to logical address groups are stored in mapping blocks allocated in the non-volatile memory. The controller limits the number of mapping blocks by garbage collection, and performs garbage collection on a source mapping block in sections. During each garbage collection section, the controller downloads valid sub mapping tables from the source mapping block to the temporary storage and then programs the valid sub mapping tables from the temporary storage to a destination mapping block. The temporary storage is repeatedly used to store valid sub mapping tables downloaded in the different garbage collection sections.

Abstract: A high-performance data storage device is disclosed, including a non-volatile memory, a controller, and a temporary storage. Sub mapping tables divided from a logical-to-physical address mapping table according to logical address groups are stored in mapping blocks allocated in the non-volatile memory. The controller limits the number of mapping blocks by garbage collection, and performs garbage collection on a source mapping block in sections. During each garbage collection section, the controller downloads valid sub mapping tables from the source mapping block to the temporary storage and then programs the valid sub mapping tables from the temporary storage to a destination mapping block. The temporary storage is repeatedly used to store valid sub mapping tables downloaded in the different garbage collection sections.

Abstract: A high-performance data storage device is disclosed. A non-volatile memory stores a logical-to-physical address mapping table that maps logical addresses recognized by a host to a physical space in the non-volatile memory. The logical-to-physical address mapping table is divided into a plurality of sub mapping tables. A memory controller utilizes temporary storage when controlling the non-volatile memory. The memory controller plans a sub mapping table area in the temporary storage to store sub mapping tables corresponding to a plurality of nodes which are linked and managed by multiple linked lists.