Patents by Inventor Bo-Yeoun Jo

Bo-Yeoun Jo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7816259
    Abstract: Deterioration of yield may be prevented when a contact in a semiconductor device is made by a method including forming a contact hole by selectively removing an insulating layer from a semiconductor substrate, depositing a barrier layer on the insulating layer and on the surface of (or in) the contact hole, depositing an initial tungsten layer on the barrier layer to at least a predetermined thickness, removing particles generated during at least one of the depositing steps, and filling the contact hole with an additional tungsten layer.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: October 19, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bo-Yeoun Jo
  • Patent number: 7651949
    Abstract: A semiconductor device may be manufactured by employing an ashing process for removing a photoresist in a process chamber, wherein the ashing process comprises: removing the photoresist for a first predetermined process time by flowing one or more oxygen and nitrogen source gases into the process chamber at first predetermined pressure, power, and temperature conditions; removing a surface portion of a polymer (e.g., from a previous etching process) for a second predetermined process time by flowing a mixture of one or more water source gases (e.g., H2O) and a fluorocarbon (e.g., CF4) into the process chamber at second predetermined pressure, power, and temperature conditions; and removing remaining photoresist for a third predetermined process time by flowing an oxygen source gas (e.g., O2) gas into the process chamber at third predetermined pressure, power, and temperature conditions.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: January 26, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bo-Yeoun Jo
  • Patent number: 7514357
    Abstract: Electrical characteristics of a semiconductor device may be enhanced by completely removing a residue such as a polymer formed in a trench when the semiconductor device is manufactured by a method including: forming a via hole and a trench on a semiconductor substrate by an etching process; coating a photoresist on an entire surface of the semiconductor substrate such that the via hole and the trench may be filled thereby; removing a polymer defect in the trench while removing the coated photoresist by a plasma treatment under predetermined process conditions; and performing a wet cleaning process so as to remove a residue of the photoresist.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: April 7, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bo-Yeoun Jo
  • Patent number: 7425511
    Abstract: A method for forming a shallow trench isolation layer that includes: forming a pad oxide on a substrate; forming a hard mask silicon nitride on the pad oxide; forming a moat pattern on the pad oxide and hard mask; etching partially the pad oxide and hard mask with the moat pattern to open the silicon nitride; and ashing process for removing the moat pattern.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: September 16, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bo Yeoun Jo
  • Patent number: 7365020
    Abstract: A method for etching an upper metal film of a capacitor, enables a safe etching of the upper metal film of a capacitor by exploiting an over-etch step. The method for etching the upper metal film of the capacitor includes the steps of forming a lower metal film, a lower nitride film, an upper metal film, and an upper nitride film on a substrate having a predetermined device formed thereon, and then forming a pattern thereover; etching the upper nitride film with CHF3, Ar and Cl2 using the pattern; over etching the upper metal film more than 50% with CHF3, Ar and N2 using the pattern; etching the upper metal film with CHF3, Ar and N2 using the pattern; and etching the lower nitride film with CHF3 and Ar using the pattern.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: April 29, 2008
    Assignee: Donbu Electronics Co., Ltd.
    Inventor: Bo Yeoun Jo
  • Patent number: 7365017
    Abstract: A method for finishing a metal line for a semiconductor device is disclosed, in which polymer generated when forming the metal line including aluminum and its alloy is effectively removed and the metal line is prevented from being eroded. A chlorine radical and a chlorine compound remaining on a surface of the metal line are removed using H2O plasma and the polymer is removed using H2O gas and HF gas not plasma. Therefore, it is possible to improve reliability and yield of the semiconductor device.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: April 29, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bo Yeoun Jo
  • Patent number: 7297607
    Abstract: A method of performing a seasoning process for a semiconductor device processing apparatus is provided by the present invention. The method includes: forming a material layer on a test wafer; coating a photoresist on the material layer; patterning the photoresist so as to expose a central region of the wafer and cover an edge region thereof; and etching the material layer exposed by the photoresist pattern.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: November 20, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bo-Yeoun Jo
  • Patent number: 7279382
    Abstract: An example method of manufacturing a semiconductor device having a capacitor includes sequentially depositing a lower metal layer, an insulating layer and an upper metal layer on a semiconductor substrate, removing a first photoresist pattern by using O2/N2 plasma, and removing polymer existing on the lower metal layer by using H2O/CF4 plasma. According to one example, the capacitor may include a lower electrode film, the capacitor insulating film and the upper electrode film.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: October 9, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bo Yeoun Jo
  • Patent number: 7247572
    Abstract: A method for fabricating a capacitor using a metal/insulator/metal (MIM) structure is disclosed. An example method for fabricating a capacitor using an MIM structure including a first metal layer, a dielectric layer, and a second metal layer etches the second metal layer and the dielectric layer in order and changes the etching conditions associated with the second metal layer prior to etching the dielectric layer.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: July 24, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bo-Yeoun Jo
  • Publication number: 20060141776
    Abstract: Electrical characteristics of a semiconductor device may be enhanced by completely removing a residue such as a polymer formed in a trench when the semiconductor device is manufactured by a method including: forming a via hole and a trench on a semiconductor substrate by an etching process; coating a photoresist on an entire surface of the semiconductor substrate such that the via hole and the trench may be filled thereby; removing a polymer defect in the trench while removing the coated photoresist by a plasma treatment under predetermined process conditions; and performing a wet cleaning process so as to remove a residue of the photoresist.
    Type: Application
    Filed: December 2, 2005
    Publication date: June 29, 2006
    Inventor: Bo-Yeoun Jo
  • Publication number: 20060141799
    Abstract: A semiconductor device may be manufactured by employing an ashing process for removing a photoresist in a process chamber, wherein the ashing process comprises: removing the photoresist for a first predetermined process time by flowing one or more oxygen and nitrogen source gases into the process chamber at first predetermined pressure, power, and temperature conditions; removing a surface portion of a polymer (e.g., from a previous etching process) for a second predetermined process time by flowing a mixture of one or more water source gases (e.g., H2O) and a fluorocarbon (e.g., CF4) into the process chamber at second predetermined pressure, power, and temperature conditions; and removing remaining photoresist for a third predetermined process time by flowing an oxygen source gas (e.g., O2) gas into the process chamber at third predetermined pressure, power, and temperature conditions.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 29, 2006
    Inventor: Bo-Yeoun Jo
  • Publication number: 20060141798
    Abstract: A method of performing a seasoning process for a semiconductor device processing apparatus is provided by the present invention. The method includes: forming a material layer on a test wafer; coating a photoresist on the material layer; patterning the photoresist so as to expose a central region of the wafer and cover an edge region thereof; and etching the material layer exposed by the photoresist pattern.
    Type: Application
    Filed: December 15, 2005
    Publication date: June 29, 2006
    Inventor: Bo-Yeoun Jo
  • Publication number: 20060094227
    Abstract: Deterioration of yield may be prevented when a contact in a semiconductor device is made by a method including forming a contact hole by selectively removing an insulating layer from a semiconductor substrate, depositing a barrier layer on the insulating layer and on the surface of (or in) the contact hole, depositing an initial tungsten layer on the barrier layer to at least a predetermined thickness, removing particles generated during at least one of the depositing steps, and filling the contact hole with an additional tungsten layer.
    Type: Application
    Filed: October 24, 2005
    Publication date: May 4, 2006
    Inventor: Bo-Yeoun Jo
  • Publication number: 20040147085
    Abstract: A method for fabricating a capacitor using a metal/insulator/metal (MIM) structure is disclosed. An example method for fabricating a capacitor using an MIM structure including a first metal layer, a dielectric layer, and a second metal layer etches the second metal layer and the dielectric layer in order and changes the etching conditions associated with the second metal layer prior to etching the dielectric layer.
    Type: Application
    Filed: December 22, 2003
    Publication date: July 29, 2004
    Inventor: Bo-Yeoun Jo