Patents by Inventor Bo-Yeun Kim
Bo-Yeun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10297308Abstract: A semiconductor device may be provided. The semiconductor device may include an address input circuit and a target address generation circuit. The address input circuit may be configured to latch a bank address and an address to generate a bank active signal and a latch address based on the execution of an active operation. The target address generation circuit may be configured to generate the latch address as a target address.Type: GrantFiled: May 4, 2018Date of Patent: May 21, 2019Assignee: SK hynix Inc.Inventor: Bo Yeun Kim
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Publication number: 20180254080Abstract: A semiconductor device may be provided. The semiconductor device may include an address input circuit and a target address generation circuit. The address input circuit may be configured to latch a bank address and an address to generate a bank active signal and a latch address based on the execution of an active operation. The target address generation circuit may be configured to generate the latch address as a target address.Type: ApplicationFiled: May 4, 2018Publication date: September 6, 2018Applicant: SK hynix Inc.Inventor: Bo Yeun KIM
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Patent number: 9990978Abstract: A semiconductor device may be provided. The semiconductor device may include an address input circuit and a target address generation circuit. The address input circuit may be configured to latch a bank address and an address to generate a bank active signal and a latch address based on the execution of an active operation. The target address generation circuit may be configured to generate the latch address as a target address.Type: GrantFiled: August 26, 2016Date of Patent: June 5, 2018Assignee: SK hynix Inc.Inventor: Bo Yeun Kim
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Publication number: 20170270997Abstract: A semiconductor device may be provided. The semiconductor device may include an address input circuit and a target address generation circuit. The address input circuit may be configured to latch a bank address and an address to generate a bank active signal and a latch address based on the execution of an active operation. The target address generation circuit may be configured to generate the latch address as a target address.Type: ApplicationFiled: August 26, 2016Publication date: September 21, 2017Inventor: Bo Yeun KIM
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Publication number: 20170242754Abstract: Semiconductor device including an input and output line control circuit may be provided. The input/output line control circuit may include a write connection circuit configured to transmit data of a write local line pair based on a write control signal. The input/output line control circuit may include a connection circuit configured to transmit data received from the write connection circuit to a write segment line pair based on a switching signal. The input/output line control circuit may be configured to transmit data of the write local line pair to the write segment line pair, based on the switching signal and the write control signal.Type: ApplicationFiled: June 1, 2016Publication date: August 24, 2017Inventors: Mun Seon JANG, Saeng Hwan KIM, Bo Yeun KIM
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Patent number: 9734888Abstract: A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address corresponding to a first external signal that is inputted at a random time, and a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation.Type: GrantFiled: February 6, 2015Date of Patent: August 15, 2017Assignee: SK Hynix Inc.Inventors: Seok-Cheol Yoon, Bo-Yeun Kim, Jae-Il Kim, Kyoung-Chul Jang
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Patent number: 9589669Abstract: A semiconductor system and semiconductor device may be provided. The semiconductor system may include a first semiconductor device configured to generate a test mode signal and configured to receive output data. The semiconductor system may include a second semiconductor device configured to enter a test mode, based on the test mode signal, and block the output data of data that is stored in redundancy memory cells connected to unrepaired redundancy word lines which are not used among redundancy word lines provided for replacing failed word lines.Type: GrantFiled: June 27, 2016Date of Patent: March 7, 2017Assignee: SK HYNIX INC.Inventors: Young Hyun Baek, Bo Yeun Kim, Sang Hee Kim, Ji Eun Jang
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Patent number: 9418725Abstract: A semiconductor device may include a common coupling block suitable for coupling a plurality of first data lines to a plurality of second data lines in response to a common control signal, which is activated regardless of a data bandwidth option mode, a first coupling block suitable for coupling a part of the plurality of second data lines to a part of a plurality of third data lines in response to a first operation control signal, a second coupling block suitable for coupling the other part of the plurality of second data lines to the other part of the plurality of third data lines in response to a second operation control signal, and a control block suitable for activating one or more of the first and second operation control signals based on the data bandwidth option mode, during a data input/output operation.Type: GrantFiled: April 7, 2015Date of Patent: August 16, 2016Assignee: SK Hynix Inc.Inventor: Bo-Yeun Kim
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Patent number: 9396786Abstract: A memory includes a plurality of word lines each coupled to one or more memory cells, an address storage unit suitable for storing an address of a word line selected for access by a control unit among the plurality of word lines at a first time point; and the control unit suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command, refreshing one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every Nth application of the refresh command where N is a natural number and selecting one or more of the plurality of word lines for access, wherein the first time point is included in time section other than a refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command.Type: GrantFiled: October 3, 2014Date of Patent: July 19, 2016Assignee: SK Hynix Inc.Inventors: Seok-Cheol Yoon, Bo-Yeun Kim, Jae-Boum Park
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Publication number: 20160133311Abstract: A semiconductor device may include a common coupling block suitable for coupling a plurality of first data lines to a plurality of second data lines in response to a common control signal, which is activated regardless of a data bandwidth option mode, a first coupling block suitable for coupling a part of the plurality of second data lines to a part of a plurality of third data lines in response to a first operation control signal, a second coupling block suitable for coupling the other part of the plurality of second data lines to the other part of the plurality of third data lines in response to a second operation control signal, and a control block suitable for activating one or more of the first and second operation control signals based on the data bandwidth option mode, during a data input/output operation.Type: ApplicationFiled: April 7, 2015Publication date: May 12, 2016Inventor: Bo-Yeun KIM
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Patent number: 9190139Abstract: A memory may include a plurality of word lines, one or more redundancy word lines for replacing one or more word lines among the plurality of word lines, a target address generation unit suitable for generating one or more target addresses using a stored address, and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, refreshing a word line selected based on the target address when the refresh command is inputted M times, and refreshing the one or more redundancy word lines whenever the refresh command is inputted N times, wherein the M and N are natural numbers.Type: GrantFiled: June 4, 2014Date of Patent: November 17, 2015Assignee: SK Hynix Inc.Inventors: Chul-Moon Jung, Bo-Yeun Kim, Saeng-Hwan Kim
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Patent number: 9190137Abstract: A memory may include a plurality of word lines coupled to one or more memory cells; a target address generation unit suitable for generating one or more target addresses using a stored address; and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, and refreshing a word line corresponding to the target address in response to the refresh command at a random time.Type: GrantFiled: June 6, 2014Date of Patent: November 17, 2015Assignee: SK Hynix Inc.Inventors: Bo-Yeun Kim, Seok-Cheol Yoon, Ji-Eun Jang
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Publication number: 20150170728Abstract: A memory may include a plurality of word lines, one or more redundancy word lines for replacing one or more word lines among the plurality of word lines, a target address generation unit suitable for generating one or more target addresses using a stored address, and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, refreshing a word line selected based on the target address when the refresh command is inputted M times, and refreshing the one or more redundancy word lines whenever the refresh command is inputted N times, wherein the M and N are natural numbers.Type: ApplicationFiled: June 4, 2014Publication date: June 18, 2015Inventors: Chul-Moon JUNG, Bo-Yeun KIM, Saeng-Hwan KIM
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Publication number: 20150162071Abstract: A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address corresponding to a first external signal that is inputted at a random time, and a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation.Type: ApplicationFiled: February 6, 2015Publication date: June 11, 2015Inventors: Seok-Cheol YOON, Bo-Yeun KIM, Jae-Il KIM, Kyoung-Chul JANG
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Publication number: 20150162067Abstract: A memory may include a plurality of word lines coupled to one or more memory cells; a target address generation unit suitable for generating one or more target addresses using a stored address; and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, and refreshing a word line corresponding to the target address in response to the refresh command at a random time.Type: ApplicationFiled: June 6, 2014Publication date: June 11, 2015Inventors: Bo-Yeun KIM, Seok-Cheol YOON, Ji-Eun JANG
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Patent number: 9018997Abstract: A semiconductor device includes conducting lines of a first group and a second group arranged in parallel, a plurality of first internal elements respectively coupled to the conducting lines of the first group and the second group and a plurality of first contact pads arranged between and along the conducting lines of the first group and the second groups, wherein at least a part of the plurality of first contact pads are respectively coupled to control terminals of the plurality of first internal elements, and the part of the plurality of first internal elements receive a plurality of first control signals through corresponding control terminals, respectively.Type: GrantFiled: December 19, 2013Date of Patent: April 28, 2015Assignee: SK Hynix Inc.Inventor: Bo-Yeun Kim
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Publication number: 20150091639Abstract: A semiconductor device includes conducting lines of a first group and a second group arranged in parallel, a plurality of first internal elements respectively coupled to the conducting lines of the first group and the second group and a plurality of first contact pads arranged between and along the conducting lines of the first group and the second groups, wherein at least a part of the plurality of first contact pads are respectively coupled to control terminals of the plurality of first internal elements, and the part of the plurality of first internal elements receive a plurality of first control signals through corresponding control terminals, respectively.Type: ApplicationFiled: December 19, 2013Publication date: April 2, 2015Applicant: SK hynix Inc.Inventor: Bo-Yeun KIM
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Publication number: 20150085564Abstract: A memory includes a plurality of word lines each coupled to one or more memory cells, an address storage unit suitable for storing an address of a word line selected for access by a control unit among the plurality of word lines at a first time point; and the control unit suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command, refreshing one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every Nth application of the refresh command where N is a natural number and selecting one or more of the plurality of word lines for access, wherein the first time point is included in time section other than a refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command.Type: ApplicationFiled: October 3, 2014Publication date: March 26, 2015Inventors: Seok-Cheol YOON, Bo-Yeun KIM, Jae-Boum PARK
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Patent number: 8848469Abstract: A semiconductor device includes a plurality of cell blocks activated in response to a plurality of selection signals, respectively, a pre-selection signal generator configured to generate a plurality of pre-selection signals corresponding to the cell blocks, respectively, and activate at least two of the pre-selection signals by decoding addresses in a multi-test mode, a selection signal controller configured to selectively activate the plurality of selection signals in response to the plurality pre-selection signals and control active periods of the activated selection signals so as not to overlap, and a decision circuit configured to decide whether or not the cell blocks activated in response to the activated selection signals are repaired in response to stored repair information and the plurality of selection signals.Type: GrantFiled: December 21, 2011Date of Patent: September 30, 2014Assignee: Hynix Semiconductor Inc.Inventors: Bo-Yeun Kim, Ji-Eun Jang
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Patent number: 8824227Abstract: A parallel test circuit of a semiconductor memory apparatus includes a memory bank which includes first and second sub banks having test global lines, respectively, and sharing a global line connected to each of the first and second sub banks. When a read command is applied during a test mode, the parallel test circuit compares data loaded in the global line to data loaded in the test global line of the second sub bank to attain a comparison result, compresses the comparison result to attain a compression signal, and outputs the compression signal as a test output signal to a pad.Type: GrantFiled: August 15, 2012Date of Patent: September 2, 2014Assignee: SK Hynix Inc.Inventors: Bo Yeun Kim, Ji Eun Jang