Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: An enhanced chip board package structure includes a chip board and a plurality of enhanced structures, which are formed in the blind openings of the non-effective region of the chip board. Each enhanced structure has an opening. The mechanical strength is reinforced by the enhanced structures without changing the whole thickness so as to overcome the problem of warping. Meanwhile, the three-dimensional stability is thus enhanced. The opening of the enhanced structure can be selectively filled with the filler such that the mechanical strength is further reinforced and the thermally conductive effect is greatly improved.

Abstract: A package substrate structure includes a substrate, a circuit layer formed on the substrate, and an ultra-thin seed layer made of an electrically conductive material and formed between the substrate and the circuit layer. The ultra-thin seed layer is advantageous to increase the adhesion between the metal bumps or the circuit lines of the circuit layer, and the substrate. Furthermore, because the seed layer is ultra thin, the metal bumps or the circuit lines on the package substrate can be made finer in line widths and line pitches, and the good yield of the substrate with fine circuit lines can be increased.

Abstract: A method for forming a package substrate with a seed layer is provided, which includes a step of etching away the metal foil laminated on the substrate, so that the substrate has a rough surface, and a step of forming an ultra-thin seed layer on the rough surface of the substrate, wherein the ultra-thin seed layer is formed along the rough surface of the substrate, and thereby the ultra-thin seed layer has a rough surface. Consequently, the adhesion between the metal bumps or circuits formed on the ultra-thin rough seed layer and the substrate can be increased. Furthermore, because the seed layer is ultra thin, the metal bumps or the circuit lines formed on the package substrate can be made finer in line widths and line pitches, and the good yield of the package substrate with fine circuit lines can be increased.

Abstract: A method for fabricating a circuit trace on a core board having a buried hole is provided. The method includes: providing a carrier plate having a detachable metal layer, an etching barrier layer, and a metal layer sequentially stacked thereon; roughening the metal layer which can be completely roughened; laminating the bonded metal layer, the etching barrier layer, the detachable metal layer and the carrier plate onto a dielectric, wherein the metal layer faces and contacts with the dielectric; and then removing the carrier plate therefrom. As such, even if the dielectric is difficult to be completely roughened, the roughened metal layer can enhance the bondability between the metal layer and the dielectric. The metal layer is processed to become the circuit trace later.