Patents by Inventor Bo Yu

Bo Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEMS AND METHODS FOR DYNAMICALLY ALLOCATING ENERGY AMONG EXCHANGEABLE ENERGY STORAGE DEVICE STATIONS
    Publication number: 20190202415
    Abstract: The present disclosure relates to methods and associated systems for managing a plurality of device-exchange stations. The method includes, for example, (1) determining a score for each of the plurality of device-exchange stations based on an availability of energy storage devices positioned in each of the device-exchange stations; (2) determining a sequence of the plurality of device-exchange stations based on the score of each of the device-exchange stations; and (3) determining a price rate for each of the device-exchange stations by mapping the sequence of the device-exchange stations to a characteristic curve corresponding to a distribution of the price rate.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 4, 2019
    Inventors: Yun-Chun Lai, Sheng-Chin Chuang, Chien-Chung Chen, I-Fen Shih, Hok-Sum Horace Luke, Bo-Yu Chu
  • MIDDLE-OF-LINE (MOL) METAL RESISTOR TEMPERATURE SENSORS FOR LOCALIZED TEMPERATURE SENSING OF ACTIVE SEMICONDUCTOR AREAS IN INTEGRATED CIRCUITS (ICs)
    Publication number: 20190195700
    Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.
    Type: Application
    Filed: February 6, 2019
    Publication date: June 27, 2019
    Inventors: Lixin Ge, Periannan Chidambaram, Bin Yang, Jiefeng Jeff Lin, Giridhar Nallapati, Bo Yu, Jie Deng, Jun Yuan, Stanley Seungchul Song
  • HIGHLY TEMPERATURE-RESISTANT GLASS FIBER AND PREPARATION METHOD THEREFOR
    Publication number: 20190185372
    Abstract: A highly temperature-resistant glass fiber and a preparation method therefor. The glass fiber comprises 62-66 wt % of SiO2, 14-19 wt % of Al2O3, 15-20 wt % of CaO, 0-2 wt % of MgO, 0-3 wt % of Fe2O3, and 0-1.2 wt % of TiO2, the total content of Na2O and K2O is 0.1-0.8 wt %. By precisely controlling the mixture of the components, the glass fiber has good resistance to high temperature and formability, and significantly increases the high-temperature softening point. The glass fiber has a forming temperature of not exceeding 1380° C., an upper limit temperature of devitrification of lower than 1280° C., and a high temperature softening temperature of 950° C. or above.
    Type: Application
    Filed: March 30, 2018
    Publication date: June 20, 2019
    Applicant: CHONGQING POLYCOMP INTERNATIONAL CORPORATION
    Inventors: Cong ZHANG, Hongbin LI, Bo YU, Yuan YAO, Bin ZHOU, Guoyun YANG, Baijiang GONG, Shaorong BAN, Lixiong HAN
  • SYSTEMS AND METHODS FOR DETERMINING STEERING PERFORMANCE
    Publication number: 20190176876
    Abstract: Methods and apparatus are provided for determining steering performance. The method includes: generating a torque disturbance signal; applying the torque disturbance signal to a torque command of the steering system; measuring a value of torque on the steering system; recording the measured value and a value associated with the torque disturbance signal; computing at least one performance metric of the steering system based on the recorded measured value and the recorded value associated with the torque disturbance signal; and selectively improving a steering system based on the at least one performance metric.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Ian Y. Hwa, Bo Yu
  • ENHANCING INTEGRATED CIRCUIT NOISE PERFORMANCE
    Publication number: 20190163864
    Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.
    Type: Application
    Filed: February 1, 2019
    Publication date: May 30, 2019
    Inventors: Xia Li, Suo Ming Pu, Xiao Feng Tang, Bo Yu
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190164767
    Abstract: A method for manufacturing a semiconductor device includes forming a first high-k dielectric layer on a semiconductor substrate; forming a second high-k dielectric layer on the first high-k dielectric layer, in which the second high-k dielectric layer includes a material different from a material of the first high-k dielectric layer; annealing the first and second high-k dielectric layers, such that the first and second high-k dielectric layers are inter-diffused; and forming a gate electrode over the second high-k dielectric layer.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 30, 2019
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ming-Hwei HONG, Juei-Nai KWO, Yen-Hsun LIN, Keng-Yung LIN, Bo-Yu YANG, Hsien-Wen WAN
  • ENHANCING INTEGRATED CIRCUIT NOISE PERFORMANCE
    Publication number: 20190163865
    Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.
    Type: Application
    Filed: February 1, 2019
    Publication date: May 30, 2019
    Inventors: Xia Li, Suo Ming Pu, Xiao Feng Tang, Bo Yu
  • Methods, apparatuses, and system for device management
    Patent number: 10298446
    Abstract: A device management method for use in a primary router, includes: establishing a management connection with a relay router; acquiring a management interface identifier from the relay router via the management connection, the management interface identifier being an identifier of an Application Programming Interface (API) in the relay router for providing a management function; and transmitting a management instruction to the relay router via the management connection, the management instruction carrying the management interface identifier and being configured to manage an electronic device connected to the relay router.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: May 21, 2019
    Assignee: Xiaomi Inc.
    Inventors: Yong Chen, Weiyang Chen, Bo Yu, Yidong Wang, Pengfei Zhang, Yu Guo
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20190148519
    Abstract: A semiconductor device and a method for forming the same are provided. The method includes forming a gate structure over a fin structure. The method further includes forming first gate spacers on opposite sidewalls of the gate structure. The method further includes forming source/drain features in the fin structure and adjacent to the first gate spacers. The method further includes performing a surface treatment process on top surfaces of the source/drain features and outer sidewalls of the first gate spacers. The method further includes depositing a contact etch stop layer (CESL) over the source/drain features and the first gate spacers. A first portion of the CESL is deposited over the top surfaces of the source/drain features at a first deposition rate. A second portion of the CESL is deposited over the outer sidewalls of the first gate spacers at a second deposition rate.
    Type: Application
    Filed: January 19, 2018
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Hsuan LEE, Bo-Yu LAI, Chi-On CHUI, Cheng-Yu YANG, Yen-Ting CHEN, Sai-Hooi YEONG, Feng-Cheng YANG, Yen-Ming CHEN
  • LOW-K GATE SPACER AND METHODS FOR FORMING THE SAME
    Publication number: 20190148514
    Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
  • Earth-boring tools and methods for forming earth-boring tools using shape memory materials
    Patent number: 10280479
    Abstract: An earth-boring tool includes a tool body, at least one cutting element, and a retaining member comprising a shape memory material (e.g., alloy, polymer, etc.) located between a surface of the tool body and a surface of the cutting element. The shape memory material is configured to transform, responsive to application of a stimulus, from a first solid phase to a second solid phase. The retaining member comprises the shape memory material in the second solid phase, and at least partially retains the at least one cutting element adjacent the tool body. The shape memory material may be trained in a first phase to a first shape, and trained in a second phase to a second shape. The retaining member may be at least partially within a cavity in the first phase, then transformed to the second phase to apply a force securing the cutting element to the tool body.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: May 7, 2019
    Assignee: Baker Hughes, a GE company, LLC
    Inventors: Bo Yu, Xu Huang, Juan Miguel Bilen, John H. Stevens, Eric C. Sullivan
  • Semiconductor structure and method for forming the same
    Patent number: 10283624
    Abstract: A semiconductor device and a method for forming the same are provided. The method includes forming a gate structure over a fin structure. The method further includes forming first gate spacers on opposite sidewalls of the gate structure. The method further includes forming source/drain features in the fin structure and adjacent to the first gate spacers. The method further includes performing a surface treatment process on top surfaces of the source/drain features and outer sidewalls of the first gate spacers. The method further includes depositing a contact etch stop layer (CESL) over the source/drain features and the first gate spacers. A first portion of the CESL is deposited over the top surfaces of the source/drain features at a first deposition rate. A second portion of the CESL is deposited over the outer sidewalls of the first gate spacers at a second deposition rate.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Chi-On Chui, Cheng-Yu Yang, Yen-Ting Chen, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Conformal transfer doping method for fin-like field effect transistor
    Patent number: 10276691
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Thermosensitive hydrogel collagenase formulations
    Patent number: 10272140
    Abstract: It is an object of the present disclosure to provide a formulation for injectable collagenase which will have extended residence time for the drug at the therapeutic targeted area for the indication being treated. It is a further object of the disclosure to provide a slow release formulation for collagenase which is compatible with the active ingredient and does not adversely affect its activity. Still a further object of the disclosure is to provide an injectable formulation for collagenase which can be effectively administered to a patient with a small size needle without exhibiting pregelation, which would interfere with the ability to deliver the required dose for treatment.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: April 30, 2019
    Assignee: BIOSPECIFICS TECHNOLOGIES CORP.
    Inventors: Bo Yu, Thomas L. Wegman
  • HUMANIZED ANTI-CD40 ANTIBODIES AND METHODS OF ADMINISTERING THEREOF
    Publication number: 20190117771
    Abstract: The present disclosure relates to anti-CD40 antibodies, such as humanized anti-CD40 antibodies, that may be used in various therapeutic, prophylactic and diagnostic methods. The antibodies generally block the ability of CD40 to bind CD154 and do so without activating the cell expressing CD40 (e.g., a B cell). The present antibodies or fragments thereof may be used to reduce complications associated with organ or tissue transplantation.
    Type: Application
    Filed: December 27, 2018
    Publication date: April 25, 2019
    Inventors: Bo Yu, Rijian Wang, Keith Reimann
  • ESTIMATING STABILITY MARGINS IN A STEER-BY-WIRE SYSTEM
    Publication number: 20190118855
    Abstract: Examples of techniques for estimating stability margins in a steer-by-wire system are disclosed. In one example implementation, a method for open-loop steer-by-wire (SbW) system linearization includes linearizing, by a processing device, an open-loop SbW system at different operating points. The method further includes determining, by the processing device, an open-loop transfer function of the op en-loop SbW system. The method further includes estimating, by the processing device, margins of stability for the open-loop SbW system. The method further includes implementing the margins of stability into a vehicle to reduce instability in a steering system of the vehicle.
    Type: Application
    Filed: October 19, 2017
    Publication date: April 25, 2019
    Inventors: Bo Yu, Ibrahim A. Badiru, Scott R. Kloess
  • LED package structure
    Patent number: 10270020
    Abstract: An LED package structure includes a first metal plate, a second metal plate, and a mold. The first metal plate has at least one first protrusion portion. The second metal plate has at least one second protrusion portion. The mold is disposed on the first metal plate and the second metal plate, in which the mold has a first side surface, a second side surface opposite to the first side surface, a third side surface, and a fourth side surface opposite to the third side surface. The first and second protrusion portion protrude respectively from the first side surface and the second side surface, and the first metal plate and the second metal plate are covered by the third side surface and the fourth side surface, in which a portion of the first side surface between the first edge and the first protrusion portion is a fracture surface.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 23, 2019
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Dao-Wei Chen, Kun-Jung Wu, Bo-Yu Ko
  • Methods for Computing Coronary Physiology Indexes Using a High Precision Registration Model
    Publication number: 20190110776
    Abstract: This invention describes methods to compute coronary physiology indexes using a high precision registration model, which consists of acquiring coronary angiography images of coronary vessels, performing intravascular imaging, and registering the coronary angiography images with intravascular images to create a high precision registration model, based upon which the coronary flow, fractional flow reserve (FFR) and index of microcirculation resistance (IMR) can be computed. The methods described in this invention to compute coronary flow, FFR, IMR are based on both coronary angiography and intravascular images, and the accuracy is better than those derived from coronary angiography alone or intravascular imaging alone, and have high practical values.
    Type: Application
    Filed: October 8, 2018
    Publication date: April 18, 2019
    Applicant: Panorama Scientific Co. Ltd
    Inventors: Bo Yu, Haibo Jia, Sining Hu, Jiannan Dai, Lei Xing, Chenyang Xu, Zhao Wang, Shuai Zhang
  • METHOD FOR MANUFACTURING GATE STACK STRUCTURE
    Publication number: 20190109202
    Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Inventors: Chun-Ting Chiang, Chi-Ju Lee, Chih-Wei Lin, Bo-Yu Su, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang
  • Display method of terminal device and terminal device
    Patent number: 10254950
    Abstract: A display method of a terminal device and a terminal device is provided. The display method of a terminal device includes: a framework layer sends a first touch point data; an application layer sends instruction information used to instruct to transfer slide drawing control rights to the framework layer and a generated display list to the framework layer after the application layer determines that the terminal device enters a sliding state according to acquired first touch point data; and the framework layer acquires second touch point data from a shared memory according to the instruction information, and draws an image according to the second touch point data and the display list. In this way, in an operation with repetitive image composition, the slide drawing control rights are transferred from an application module to a framework module, improving a response speed of a terminal system.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: April 9, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Bo Yu, Jianbin Qiu