Abstract: A transmission line can include a first conductive line, a second conductive line, a signal line disposed between the first conductive line and the second conductive line, with a first gap between the signal line and the first conductive line, and a second gap between the signal line and the second conductive line. A first shield can be disposed directly over a portion of the first gap, and a second shield can be disposed directly over a portion of the second gap. A slot can separate the first shield from the second shield. The transmission line can be a coplanar waveguide.

Abstract: An antenna correcting system is provided. The antenna correction system compares amplitudes of antenna signals that are emitted or received respectively by a plurality of antenna units with each other to select one of the amplitudes as target amplitude. The antenna correction system corrects the amplitude of each of the antenna signals according to the target amplitude. As a result, the amplitudes of the antenna signals are the same as each other or approximate to each other. After the amplitudes of the antenna signals are corrected, the antenna correction system compares phases of the antenna signals with each other to select one of the phases as a target phase. The antenna correction system corrects the phase of each of the antenna signals according to the target phase. As a result, the phases of the antenna signals are the same as each other or approximate to each other.

Abstract: A method of correcting a GPS vehicle trajectory of a vehicle on a roadway for a high-definition map is provided. The method comprises receiving first bitmap data from a first sensor of a first vehicle to create a plurality of first multi-layer bitmaps for the first vehicle using the first bitmap data and receiving second bitmap data from a plurality of second sensors of a plurality of second vehicles to create a plurality of second multi-layer bitmaps. The method further comprises creating first probability density bitmaps and an overall probability density bitmap with a probability density estimation, and matching an image template from each of the first probability density bitmaps with the overall probability density bitmap to define match results. The method further comprises combining the match results to define combined utility values and determining the maximal utility value with the combined utility values.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are presented. In embodiments the methods of manufacturing include depositing a first bonding layer on a first substrate, wherein the first substrate comprises a semiconductor substrate and a metallization layer. The first bonding layer and the semiconductor substrate are patterned to form first openings. A second substrate is bonded to the first substrate. After the bonding the second substrate, the second substrate is patterned to form second openings, at least one of the second openings exposing at least one of the first openings. After the patterning the second substrate, a third substrate is bonded to the second substrate, and after the bonding the third substrate, the third substrate is patterned to form third openings, at least one of the third openings exposing at least one of the second openings.

Abstract: Provided are a tank support jig and a tank cleaning method. The tank support jig for supporting a cylindrical tank includes a curved body having a first end and a second end that face with an interval in between; and a connecting member disposed across the interval, the connecting member connecting the first end and the second end of the curved body such that the interval is adjustable, in which the curved body and the connecting member form an annular structure for the tank that is to be placed horizontally inside the annular structure with the curved body in close contact with at least part of an outer circumferential face of the tank along a circumferential direction of the tank.

Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: Methods and structures for modulating an inner spacer profile include providing a fin having an epitaxial layer stack including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. Thereafter, in some examples, the method includes conformally depositing a dielectric layer to substantially fill the first gap between the adjacent semiconductor channel layers. In some cases, the method further includes etching exposed lateral surfaces of the dielectric layer to form an etched-back dielectric layer that defines substantially V-shaped recesses. In some embodiments, the method further includes forming a substantially V-shaped inner spacer within the substantially V-shaped recesses.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: A media docking device includes an input module, an output module and a processing module. The input module is electrically connected to a media source device for receiving media data. The output module is electrically connected to a media play device. The processing module determines if an instruction is received from the media source device or a remote device. If the instruction is not received, the processing module transfers the media data to the output module to transmit to the media play device. If the instruction is received, the processing module limits a transmission of the media data according to the instruction, such that the media data will not be completely played by the media play device.

Abstract: A media docking device includes an input circuit, an output circuit and a processing circuit. The input circuit is electrically connected to a media source device for receiving media data. The output circuit is electrically connected to a media play device. The processing circuit is electrically connected to the input circuit and the output circuit. The processing circuit determines if a verification procedure is passed. If the verification procedure is passed, the processing circuit transfers the media data to the media play device. If the verification procedure is not passed, the processing circuit limits a transmission of the media data, such that the media data will not be completely played by the media play device.

Abstract: A packaging device includes a first circuit substrate and a second circuit substrate that are electrically connected. The first circuit substrate includes a first line layer and a first insulation layer that are sequentially stacked, and a first electronic component is disposed on the first circuit substrate. The second circuit substrate includes a second line layer and a second insulation layer that are sequentially stacked, and a second electronic component is disposed on the second circuit substrate. A thermal conductivity of the first insulation layer is higher than a thermal conductivity of the second insulation layer. This application further provides a packaging module and an electronic device in which the packaging device is used. The packaging device in this application, the first insulation layer and the second insulation layer with different thermal conductivities are targetedly configured, and layouts of the first circuit substrate and the second circuit substrate are flexible.

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: A global positioning system (GPS)-bias detection and reduction system including a GPS-bias model having GPS statistical data creating a database representing data collected from a vehicle group having thousands or multiple thousands of vehicles saved in a database. At least one newly collected vehicle GPS data point is compared to the GPS statistical data to reduce negative effects of GPS-bias and to update the vehicle GPS-bias correction based on a previous GPS-bias model. A selected road node and a segment of a roadway have a map matching performed using a nearest service from a collection location of the GPS statistical data. A GPS-bias is calculated using a look-up of the database. An estimated horizontal position error (EHPE) defining a quality indicator is applied to distinguish a good quality GPS statistical data from a poor quality GPS statistical data.

Abstract: An apparatus comprising an interface, a structured light projector and a processor. The interface may receive pixel data. The structured light projector may generate a structured light pattern. The processor may process the pixel data arranged as video frames, perform operations using a convolutional neural network to determine a binarization result and an offset value and generate disparity and depth maps in response to the video frames, the structured light pattern, the binarization result, the offset value and a removal of error points. The convolutional neural network may perform a partial block summation to generate a convolution result, compare the convolution result to a speckle value to determine the offset value, generate an adaptive result in response to performing a convolution operation, compare the video frames to the adaptive result to generate the binarization result for the video frames, and remove the error points from the binarization result.

Abstract: A system within an ego vehicle for robust association of a physical identity and a virtual identity of a target vehicle includes a data processor, including a wireless communication module and a visible light communication module, positioned within an ego vehicle, and a plurality of perception sensors, positioned within the ego vehicle and adapted to collect data related to a physical identity of the target vehicle and to communicate the data related to the physical identity of the target vehicle to the data processor via a communication bus, the data processor within the ego vehicle adapted to receive, via a wireless communication channel, data related to a virtual identity of the target vehicle, associate the physical identity of the target vehicle with the virtual identity of the target vehicle, and initiate, via the wireless communication channel and a visible light communication channel, a challenge-response protocol between the ego vehicle and the target vehicle.

Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

Abstract: Disclosed are techniques for wireless communication. In an aspect, a UE sets up an evolved packet system fallback (EPSFB) call procedure that is associated with network-configured inter-frequency measurements to be performed by the UE at a first inter-frequency measurement interval. The UE punctures some or all of the network-configured inter-frequency measurements during the EPSFB call procedure.

Abstract: A method of creating a high-definition (HD) map of a roadway includes receiving a multi-layer probability density bitmap. The multi-layer probability density bitmap represents a plurality of lane lines of the roadway sensed by a plurality of sensors of a plurality of vehicles. The multi-layer probability density bitmap includes a plurality of points. The method further includes recursively conducting a hill climbing search using the multi-layer probability density bitmap to create a plurality of lines. In addition, the method includes creating the HD map of the roadway using the plurality of lines determined by the hill climbing search.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.