Abstract: Apparatus for presetting an electric pulse counter to a given count without any action on its parallel input terminals and/or its parallel output terminals. The apparatus comprises a pulse generator which is connected, during a preset operation, to the count input of the counter through an electronic gate. The electronic gate is controlled by an auxiliary circuit. In one embodiment, the auxiliary circuit comprises as many voltage comparators as flip-flops in the counter. The voltage comparators enable the electronic gate as long as the states of the flip-flops are different from the desired states. In another embodiment, the auxiliary circuit mainly comprises a divider by N, N being the desired count. In a first step, the divider is reset and the counter is caused to count up to its maximum count and to deliver an overflow pulse when it resets. In a second step starting with the overflow pulse, both counter and divider count up from zero and the electronic gate is closed when the divider reaches the N-count.