Abstract: A method placing items routing wiring pursuant to integrated circuit specifications to create an integrated circuit design. Once the initially placed design is legalized, rather that just starting wiring routing, the method identifies books in the integrated circuit design which contain blocked items. The method allows the routing process to be paused temporarily, and for the items to be moved to a certain extent. This movement process is controlled (limited according to signal power output by the associated books) so that the timing of the integrated circuit design is not affected by any such “mid-routing” movement. If the books do not have any blocked items, the process continues to route wires between the items and the books. If at any point before or during the routing of the wires it is found that the books do have blocked items, the process pauses the routing of the wires and performs any number of different processes to solve the blocked item situation (unblock the blocked items).

Abstract: Device, system and method of correcting an integrated circuit design. For example, a method includes receiving a list of one or more root points for an active netlist that requires logic correction, wherein the root points correlate between elements of the active netlist and elements of a re-synthesized netlist that is based on a high-level correction for the integrated circuit design; automatically identifying in the active netlist a driving logic cone for at least one of the root points; and automatically identifying in the re-synthesized netlist a driving logic cone for the respectively correlated root point, including one or more corrected logic elements that correspond to the one or more identified flawed logic elements.

Abstract: A method placing items routing wiring pursuant to integrated circuit specifications to create an integrated circuit design. Once the initially placed design is legalized, rather that just starting wiring routing, the method identifies books in the integrated circuit design which contain blocked items. The method allows the routing process to be paused temporarily, and for the items to be moved to a certain extent. This movement process is controlled (limited according to signal power output by the associated books) so that the timing of the integrated circuit design is not affected by any such “mid-routing” movement. If the books do not have any blocked items, the process continues to route wires between the items and the books. If at any point before or during the routing of the wires it is found that the books do have blocked items, the process pauses the routing of the wires and performs any number of different processes to solve the blocked item situation (unblock the blocked items).

Abstract: Reducing turn around time of engineering change orders in ASIC re-spin design includes finding, on the fly, all corresponding boundary points of storage gate elements indicated by engineering change orders to be either added, deleted or renamed. Boolean equivalence tools are used between an old spin ASIC design and a new ASIC design netlist, as well as between the new ASIC design netlist and a new re-spin ASIC design to obtain failing boundary storage gate elements and perform one or more of adding, deleting or modifying or renaming all failing boundary storage gate elements, so they pass correspondence tests. Engineering change order scripts are automatically generated to indicate which storage logic gate elements are to be added, deleted or modified and the scripts are applied to the old ASIC design to obtain the new re-spin ASIC design, after which ASIC flow gate level fixes are applied to synthesized storage gate elements.

Abstract: Device, system and method of correcting an integrated circuit design. For example, a method includes receiving a list of one or more root points for an active netlist that requires logic correction, wherein the root points correlate between elements of the active netlist and elements of a re-synthesized netlist that is based on a high-level correction for the integrated circuit design; automatically identifying in the active netlist a driving logic cone for at least one of the root points; and automatically identifying in the re-synthesized netlist a driving logic cone for the respectively correlated root point, including one or more corrected logic elements that correspond to the one or more identified flawed logic elements.

Abstract: A novel system and procedure for placement and validation of I/O pins within an ASIC package module. The system reads and a plurality of data files containing chip design, technology and package related information. The parsed data is stored in a single I/O assignment information database that functions to store and organize all the data from all chip design, technology and package files. Access to the database is controlled by three sets of keys, with each key in each set being unique. The three sets of keys include: pin name, package pin coordination and Controlled Collapse Chip Connection (C4) on a flip chip area array packaging or IO slot (i e. chip wire bond connection). A dynamic graphical view of the package pins is built using these three keys and the contents of the I/O assignment information database. Users enter pin assignments data and, in response, the system validates the data against a set (of technology constraints and updates the assignment database accordingly.