Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.

Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.

Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.

Abstract: A system includes a dynamic random-access memory (DRAM); and a storage device comprising a power source and a persistent store. The storage device is configured to provide reserve power to the DRAM. Data stored in the DRAM is transferred to a reserved storage in the persistent store of the storage device in a power loss event using the reserve power.

Abstract: An embodiment includes a storage device, comprising: a memory; and a controller including a memory interface coupled to the memory, the controller configured to: receive write data to write to an address associated with first data stored in the memory and a first differentially compressed value stored in the memory; calculate a second differentially compressed value based on the write data and the first data; store the second differentially compressed value in the memory; and change the association of the address to reference the second differentially compressed value instead of the first differentially compressed value.

Abstract: A deduplication memory module, which is configured to internally perform memory deduplication, includes a hash table memory for storing multiple blocks of data in a hash table array including hash tables, each of the hash tables including physical buckets and a plurality of virtual buckets each including some of the physical buckets, each of the physical buckets including ways, an address lookup table memory (ALUTM) including a plurality of pointers indicating a location of each of the stored blocks of data in a corresponding one of the physical buckets, and a buffer memory for storing unique blocks of data not stored in the hash table memory when the hash table array is full, a processor, and memory, wherein the memory has stored thereon instructions that, when executed by the processor, cause the memory module to exchange data with an external system.

Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.

Abstract: A system includes a dynamic random-access memory (DRAM); and a storage device comprising a power source and a persistent store. The storage device is configured to provide reserve power to the DRAM. Data stored in the DRAM is transferred to a reserved storage in the persistent store of the storage device in a power loss event using the reserve power.

Abstract: A deduplication memory module, which is configured to internally perform memory deduplication, includes a hash table memory for storing multiple blocks of data in a hash table array including hash tables, each of the hash tables including physical buckets and a plurality of virtual buckets each including some of the physical buckets, each of the physical buckets including ways, an address lookup table memory (ALUTM) including a plurality of pointers indicating a location of each of the stored blocks of data in a corresponding one of the physical buckets, and a buffer memory for storing unique blocks of data not stored in the hash table memory when the hash table array is full, a processor, and memory, wherein the memory has stored thereon instructions that, when executed by the processor, cause the memory module to exchange data with an external system.

Abstract: An embodiment includes a storage device, comprising: a memory; and a controller including a memory interface coupled to the memory, the controller configured to: receive write data to write to an address associated with first data stored in the memory and a first differentially compressed value stored in the memory; calculate a second differentially compressed value based on the write data and the first data; store the second differentially compressed value in the memory; and change the association of the address to reference the second differentially compressed value instead of the first differentially compressed value.

Abstract: A ground rod includes first and second ends connected by a shaft portion. The first end has an auger configuration permitting it to be drilled into the ground. The opposite end is adapted to attached to either an electric drill or an impact wrench. This drastically reduces the time required to drive the ground rod into the ground. In an alternate embodiment, the ground rod also adapted to attach to a handle which allows it to be manually inserted or removed from the ground.

Abstract: A ground rod includes first and second ends connected by a shaft portion. The first end has an auger configuration permitting it to be drilled into the ground. The opposite end is adapted to attached to either an electric drill or an impact wrench. This drastically reduces the time required to drive the ground rod into the ground. In an alternate embodiment, the ground rod also adapted to attach to a handle which allows it to be manually inserted or removed from the ground.

Abstract: A power driven fish tape includes a handle and a spool. The handle rides along the peripheral surface of the spool and feeds a metal strip fish line into or out of the spool. The handle includes a first gear which drives a second gear on the spool. The drive gear can be attached to a portable drill which permits the fish tape to be fed or rewound using the power drill.

Abstract: A method and apparatus for efficient propagation of attribute bits in an instruction decoding pipeline. Attribute bits associated with instructions are manipulated in a like manner to the instructions in an instruction decode pipeline. The pipeline has three pipe stages. Some of the attribute bits are generated in the first pipe stage but not used until the third pipe stage. A prefetch buffer stores prefetched instruction bytes. Attribute bits for each prefetched instruction byte are generated and stored in an attribute buffer in locations corresponding to the instruction bytes stored in the prefetch buffer. A code rotator selects two sequential instructions from the prefetch buffer and stores them in an instruction FIFO for later decoding and execution in the pipeline. In like manner and in parallel, an attribute rotator selects two sets of attribute bits corresponding to the selected instructions and stores them in the instruction FIFO.

Abstract: A method and apparatus for fast decoding of 00H and 0FH mapped instructions. A set of instruction bytes are selected for length decoding. Instruction bytes that contain no length information, such as 0FH opcode bytes in the Intel architecture instruction set, are detected and shifted out of the set before length decoding to determine the length of an instruction is performed on the set. Removing instruction bytes that contribute no length information allows the length decoder logic to be optimized for size and speed. In one embodiment, parallel length decoder sets that each include a detector, shifter, and length decoder operate in parallel on a line of instruction bytes prefetched from an instruction cache. In one embodiment, the length decoders are PLAs (programmable logic arrays) that are combined with separate shifters and detectors logic. This embodiment advantageously allows smaller PLA length decoders.