Abstract: A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory. Thus, when data words are transferred between storage memory and the processing array, a mechanism orthogonally transposes the data words.

Abstract: A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.

Abstract: A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Abstract: A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory. Thus, when data words are transferred between storage memory and the processing array, a mechanism orthogonally transposes the data words.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory. Thus, when data words are transferred between storage memory and the processing array, a mechanism orthogonally transposes the data words.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability for selected write data in a bit line section to be logically combined (e.g. logically ANDed) with the read result on a read bit line, as if the write data were the read data output of another computational memory cell being read during the read operation. When accumulation logic is implemented in the bit line sections, the implementation and utilization of additional read logic circuitry provides a mechanism for selected write data in a bit line section to be used as the data with which the read result on the read bit line accumulates, before the newly accumulated result is captured and stored in the bit line section's read register.

Abstract: A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.

Abstract: A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to inhibit writes in selective bit line sections on per-write operation basis to enhance the computational capability of the bl-sects. The read and write data processing apparatus and method also provides a mechanism to inhibit the read bit line pre-charge in selective bit line sections for an extended period of time to save power when pre-charge circuitry is implemented on the read bit line. The read and write data processing apparatus and method also provides a mechanism to inhibit writes to memory cells in selective bl-sects for an extended period of time, to save power.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.