Abstract: A ROM memory array comprises a doped silicon substrate having a surface with a first array of parallel bitlines formed in the substrate at the surface with an array of channel regions between the bitlines. A dielectric layer is formed on the substrate with a wordline array composed of transversely disposed parallel conductors formed on the dielectric layer, with the bitlines and the channel regions and the wordline array forming an array of field effect transistors. A gate oxide layer is formed over the wordlines. A thin film polysilicon storage plane is formed over the gate oxide layer with a second array of alternating parallel bitlines and channel regions formed in the thin film polysilicon storage plane. The second array of bitlines and channel regions is orthogonally disposed relative to the wordline array and the second array of bitlines is formed in a storage plane over an interpolysilicon oxide dielectric isolation layer.