Patents by Inventor Bob Martell

Bob Martell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thick metal layer integrated process flow to improve power delivery and mechanical buffering
    Publication number: 20060076678
    Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
    Type: Application
    Filed: November 16, 2005
    Publication date: April 13, 2006
    Inventors: Sarah Kim, Bob Martell, David Ayers, R. List, Peter Moon, Steven Towle, Anna George
  • Thick metal layer integrated process flow to improve power delivery and mechanical buffering
    Patent number: 6977435
    Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: December 20, 2005
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, Bob Martell, Dave Ayers, R. Scott List, Peter Moon, Anna M. George, legal representative, Steven Towle, deceased
  • Thick metal layer integrated process flow to improve power delivery and mechanical buffering
    Publication number: 20050051894
    Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
    Type: Application
    Filed: September 9, 2003
    Publication date: March 10, 2005
    Inventors: Sarah Kim, Bob Martell, David Ayers, R. List, Peter Moon, Steven Towle, Anna George