Abstract: A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data.

Abstract: A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data.

Abstract: A read/write timing generator includes a read/write signal generator for generating a read/write signal in response to the media event trigger of a disk drive and synchronized to a read/write bit clock. A read/write symbol clock generator adjusts a read/write symbol clock based on the read/write signal and the read/write bit clock.

Abstract: A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data.

Abstract: In a multiple-CPU, dynamic path allocation environment. The environment, several devices, such as input/output (I/O) devices, may be accessed through one of a plurality of dynamically configured paths from the CPU. Each path includes a channel, from the CPU, connected to a director. The director, in turn, is connected through respective control module interfaces, to a plurality of control modules, which control modules are used to access a string of devices. The connection method, carried out under control of the director, includes simultaneously polling all of the control modules to determine if any have devices attached thereto that are ready to be connected to the CPU. A response from the control modules, all received simultaneously at the director, identifies the CPU channel through which the connection is to be made. The specific address of the device to be connected is then determined, and the desired connection from the CPU to the device is completed.