Abstract: A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).

Abstract: A semiconductor device includes a first transistor (52) and gated diode (50) formed at a face of a semiconductor layer (56). The first transistor (52) includes a source region (60a), a drain region (60b), a gate oxide layer (62), and a conductive gate (64). The gated diode (54) includes a first moat region (66a), a second moat region (66b), a gate oxide layer (68), and a conductive gate (70). A first conductor (77) connects the conductive gate (70) of the gated diode (54) to the semiconductor layer (56) and a second conductor (76) connects the moat regions (66a, 66b) of the gated diode (54) to the conductive gate (64) of the first transistor (52). Gated diode (54) has a reduced breakdown voltage relative to the gate oxide layer (62) of first transistor (52) and thus establishes a leakage path to semiconductor layer (56) to direct leakage current to semiconductor layer (56), thereby inhibiting charge from accumulating on the gate oxide layer (62) of first transistor (52).

Abstract: A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).