Abstract: A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

Abstract: A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

Abstract: The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for fabricating a high power/logic complementary bipolar/MOS/DMOS (CBiCMOS) integrated circuit. The process steps for fabricating the novel integrated circuit combines on the same substrate complementary high power, logic/analog bipolar transistors with complementary MOSGVm devices and DMOSFET devices. The present invention optimizes the characteristics of these different transistors in a single process flow. The present high power/logic CBiCMOS multiepitaxial process results in device structures having distinct technical advantages over prior art processes and structures heretofore known.

Abstract: An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground region extending from the substrate to the third epitaxial layer in a first tank region and extending through the first and second epitaxial layers. A power bipolar transistor is formed in the first tank region. P isolation areas extending from the surface of the third epitaxial layer to the P ground region isolate the bipolar transistor from other tank region on the same substrate in which N and P channel MOSFETS are formed.