Abstract: An intelligent programmable process control system for controlling industrial processing and manufacturing equipment and the like utilizes a unique system of cooperating dual microprocessors. A digital microprocessor is utilized for digital computation and for controlling the analog portion of the processing equipment, and a boolean microprocessor is utilized for sequencing and for controlling the on/off states of devices located along the process in response to the on/off states of sensors located along the process according to a sequence of boolean logic functions. The digital microprocessor has overall supervisory control. Common memory provides a communication link between the two microprocessors. An arbitration circuit for resolving simultaneous or phased access to memory by the two microprocessors is provided. In addition, a circuit is provided for accomplishing parallel digital input/output functions, again accessible by both microprocessors.

Abstract: An intelligent programmable process control system for controlling industrial processing and manufacturing equipment and the like utilizes a unique system of cooperating multiple processors. A digital processor is utilized for controlling the analog portion of the processing equipment, and a boolean processor is utilized for sequencing and controlling the on/off states of controllable devices. Along the process communication means is provided for communications between the processors. In one embodiment, a circuit is provided for accomplishing parallel digital I/O, accessible by the digital processor for additional control of the analog processing equipment.

Abstract: An intelligent programmable process control system for controlling industrial processing and manufacturing equipment and the like utilizes a unique system of cooperating multiple microprocessors. A multi-bit microprocessor is utilized for controlling the analog portion of the processing equipment, and a single-bit microprocessor is utilized for sequencing. The control processor has overall supervisory control. An arbitration circuit for resolving simultaneous or phased access to memory by the two microprocessors is provided. In addition, a circuit is provided for accomplishing parallel I/O, again accessible by both microprocessors. In one embodiment, means for linking arithmetic functions and non-arithmetic (logic) functions within a boolean-type instruction set is provided.

Abstract: A data processor such as a programmable logic controller utilizes a read-only-memory boolean logic processor for generating solutions to complex boolean equations. The read-only-memory processor includes a plurality of address inputs for selectively addressing memory locations thereof in accordance with applied boolean data and multi-bit instructions. The contents of the addressed memory location represents the solution or partial solution to a boolean equation. A memory, in the form of a push-down stack reversible serial storage means, is coupled to the output of the processor for receiving and storing the single-bit partial solutions, and is coupled to an address input of the processor for transferring partial solutions stored therein to the processor means for further processing.

Abstract: A variable module memory, particularly suitable for use in a programmable controller, includes a set of up-to-N memory modules each for storing a plurality of words of n bits. N receptacle means are provided for receiving the set of memory modules and for coupling the received memory modules to a common serial bus. Control means is provided, coupled via said receptacle means, to said up-to-N memory modules for providing address signals for selectively addressing the words of a selected memory module to provide the contents stored therein serially to said common serial bus. A pull-up resistor connecting a predetermined voltage to a common serial bus detects the absence of memory modules in the receptacles and forces the serial bus to a predetermined binary state for all bits or all words for a vacant receptacle means.

Abstract: A programmable logic controller has input elements sampled to determine status in each of multicomponent lines of a relay ladder network. Output elements in the network connect power voltage sources to power utilization units and disconnect the same in accordance with a programmed set of instructions stored in a controller memory to satisfy operating conditions required of the ladder network. Sample means sequentially generate a set of one bit words, one word representing the state of each of the input elements. A set of one bit output control states is generated, one state for each output element in dependence upon the states of the input elements. Timing means operable once each half cycle of the power voltage initiates generation and storage in a semiconductor read/write image register of one bit input words and output control states.

Abstract: A programmable logic controller implemented in semiconductor integrated circuits which contains a memory for storing multi bit instructions and one bit data words with a processor selectively coupled to the memory for operating on the data in accordance with the instruction. A one bit word width push down stack is selectively connected to the processor for storing partial solutions to processor computations. The partial solutions are read from the stack in reverse order to entry thereof in response to completion of calculations of another part of the computations. The solution to the other part is combined with a partial solution retrieved from the push down stack.